3-8ÒëÂëÆ÷µÄVHDLÉè¼Æ ÏÂÔØ±¾ÎÄ

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3-8ÒëÂëÆ÷µÄVHDLÉè¼Æ 1.ʵÌå¿òͼ

2.³ÌÐòÉè¼Æ

ÕýÈ·µÄ³ÌÐò LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY DECODER38A IS

PORT(A2,A1,A0,S1,S2,S3:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY DECODER38A;

ARCHITECTURE ONE OF DECODER38A IS SIGNAL S: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN

S<=A2&A1&A0&S1&S2&S3; WITH S SELECT

Y<=\ \ \ \ \ \ \

\ \END ARCHITECTURE ONE; 3.·ÂÕæ²¨ÐÎͼ

4.·ÂÕæ²¨ÐηÖÎö

µ±S1 S2 S3=100ʱ£¬Ö»Óе±A2 A1 A0=111ʱ£¬Y[7]²ÅÊä³öµÍµçƽ£¬·ñÔòΪ¸ßµçƽ£¬µ±A2 A1 A0=110ʱ£¬Y[6]²ÅÊä³öµÍµçƽ£¬·ñÔòΪ¸ßµçƽ£¬µ±A2 A1 A0=101ʱ£¬Y[5]²ÅÊä³öµÍµçƽ£¬·ñÔòΪ¸ßµçƽ£¬Y[4]µ½Y[0]ͬÀí¡£¿É¼û¸Ã³ÌÐòÉè¼ÆµÄÊÇ3-8ÒëÂëÆ÷

Èý¡¢¹²Ñô¼«ÊýÂë¹ÜÆß¶ÎÏÔʾÒëÂëÆ÷µÄVHDLÉè¼Æ 1.ʵÌå¿òͼ

2.³ÌÐòÉè¼Æ

ÕýÈ·µÄ³ÌÐò LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY DISPLAY_DECODER IS PORT(A3,A2,A1,A0:IN STD_LOGIC;

Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END ENTITY DISPLAY_DECODER;

ARCHITECTURE ONE OF DISPLAY_DECODER IS SIGNAL S: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

S<=A3&A2&A1&A0; WITH S SELECT

Y<=\ \ \ \ \ \ \ \ \ \ \END ARCHITECTURE ONE; 3.·ÂÕæ²¨ÐÎͼ