基于FPGA的正弦信号发生器设计—毕业设计 下载本文

内容发布更新时间 : 2024/12/23 5:55:47星期一 下面是文章的全部内容请认真阅读。

--波形ROM

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ROM IS

PORT(ADDER:IN STD_LOGIC_VECTOR(7 DOWNTO 0); DAOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY ROM;

ARCHITECTURE ART OF ROM IS BEGIN

PROCESS(ADDER) IS BEGIN CASE ADDER IS

when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\

- - 34 - -

when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\

- - 35 - -

when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\

- - 36 - -

when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\

- - 37 - -

when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\

- - 38 - -