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when \ dp<=dp2(0); when others=> dp<='1'; end case; end process;

process(data) begin case data is when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when others=>seg<=\ end case; end process; end Behavioral;

7.top程序：

library ieee;

use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM;

use UNISIM.Vcomponents.ALL;

entity top_fan is

port ( ce_liang : in std_logic; clk : in std_logic;

s : in std_logic_vector (2 downto 0); cnte_5 : out std_logic; cnte_6 : out std_logic; dot_out : out std_logic; light_out : out std_logic; over_out : out std_logic;

seg : out std_logic_vector (6 downto 0); sel : out std_logic_vector (5 downto 0));

end top_fan;

architecture BEHAVIORAL of top_fan is signal cnte_1 : std_logic; signal cnte_2 : std_logic; signal cnte_3 : std_logic; signal cnte_4 : std_logic; signal cnte_7 : std_logic;

signal cnte_9 : std_logic_vector (3 downto 0); signal cnte_10 : std_logic_vector (3 downto 0); signal cnte_11 : std_logic_vector (3 downto 0); signal cnte_12 : std_logic_vector (3 downto 0); signal cnte_13 : std_logic_vector (3 downto 0); signal cnte_14 : std_logic_vector (3 downto 0); signal cnte_15 : std_logic_vector (3 downto 0); signal cnte_16 : std_logic_vector (3 downto 0); signal cnte_17 : std_logic_vector (3 downto 0); signal cnte_18 : std_logic_vector (3 downto 0); signal cnte_19 : std_logic_vector (3 downto 0); signal cnte_20 : std_logic_vector (3 downto 0); signal cnte_5_DUMMY : std_logic; signal cnte_6_DUMMY : std_logic; signal light_out_DUMMY : std_logic; component control

port ( insignal : in std_logic; gate : out std_logic; latch : out std_logic; reset : out std_logic); end component;

component counter_10

port ( ce_signal : in std_logic; clr : in std_logic; en : in std_logic; over_l : out std_logic;

cn1 : out std_logic_vector (3 downto 0); cn2 : out std_logic_vector (3 downto 0); cn3 : out std_logic_vector (3 downto 0); cn4 : out std_logic_vector (3 downto 0); cn5 : out std_logic_vector (3 downto 0); cn6 : out std_logic_vector (3 downto 0)); end component;

component div_f

port ( clk : in std_logic; fp_10 : out std_logic; fp_100 : out std_logic; fp_1k : out std_logic); end component;

component sele

port ( f1 : in std_logic; f10 : in std_logic; f100 : in std_logic;

s : in std_logic_vector (2 downto 0); fref : out std_logic;

dp1 : out std_logic_vector (2 downto 0)); end component;

component shao_miao

port ( f1k : in std_logic;

dp2 : in std_logic_vector (2 downto 0); data1 : in std_logic_vector (3 downto 0); data2 : in std_logic_vector (3 downto 0); data3 : in std_logic_vector (3 downto 0); data4 : in std_logic_vector (3 downto 0); data5 : in std_logic_vector (3 downto 0); data6 : in std_logic_vector (3 downto 0); dp : out std_logic;

xs_out : out std_logic_vector (5 downto 0); seg : out std_logic_vector (6 downto 0)); end component;

component suo_cun

port ( latch_in : in std_logic; over_in : in std_logic;

data_in1 : in std_logic_vector (3 downto 0); data_in2 : in std_logic_vector (3 downto 0); data_in3 : in std_logic_vector (3 downto 0); data_in4 : in std_logic_vector (3 downto 0); data_in5 : in std_logic_vector (3 downto 0); data_in6 : in std_logic_vector (3 downto 0); over_out : out std_logic;

data_out1 : out std_logic_vector (3 downto 0); data_out2 : out std_logic_vector (3 downto 0); data_out3 : out std_logic_vector (3 downto 0); data_out4 : out std_logic_vector (3 downto 0); data_out5 : out std_logic_vector (3 downto 0);

data_out6 : out std_logic_vector (3 downto 0)); end component; begin

cnte_5 <= cnte_5_DUMMY; cnte_6 <= cnte_6_DUMMY; light_out <= light_out_DUMMY; Part_1 : control

port map (insignal=>cnte_4,

gate=>light_out_DUMMY, latch=>cnte_6_DUMMY, reset=>cnte_5_DUMMY);

Part_2 : counter_10

port map (ce_signal=>ce_liang, clr=>cnte_5_DUMMY, en=>light_out_DUMMY,

cn1(3 downto 0)=>cnte_9(3 downto 0), cn2(3 downto 0)=>cnte_10(3 downto 0), cn3(3 downto 0)=>cnte_11(3 downto 0), cn4(3 downto 0)=>cnte_12(3 downto 0), cn5(3 downto 0)=>cnte_13(3 downto 0), cn6(3 downto 0)=>cnte_14(3 downto 0), over_l=>cnte_7);

Part_3 : div_f

port map (clk=>clk,

fp_1k=>cnte_3, fp_10=>cnte_1,

fp_100=>cnte_2); Part_4 : sele

port map (f1=>cnte_1, f10=>cnte_2, f100=>cnte_3,

s(2 downto 0)=>s(2 downto 0),

dp1(2 downto 0)=>cnte_21(2 downto 0), fref=>cnte_4); Part_5 : shao_miao

port map (data1(3 downto 0)=>cnte_15(3 downto 0), data2(3 downto 0)=>cnte_16(3 downto 0), data3(3 downto 0)=>cnte_17(3 downto 0), data4(3 downto 0)=>cnte_18(3 downto 0), data5(3 downto 0)=>cnte_19(3 downto 0), data6(3 downto 0)=>cnte_20(3 downto 0),

dp2(2 downto 0)=>cnte_21(2 downto 0), f1k=>cnte_3, dp=>dot_out,

seg(6 downto 0)=>seg(6 downto 0),

xs_out(5 downto 0)=>sel(5 downto 0)); Part_6 : suo_cun

port map (data_in1(3 downto 0)=>cnte_9(3 downto 0), data_in2(3 downto 0)=>cnte_10(3 downto 0), data_in3(3 downto 0)=>cnte_11(3 downto 0), data_in4(3 downto 0)=>cnte_12(3 downto 0), data_in5(3 downto 0)=>cnte_13(3 downto 0), data_in6(3 downto 0)=>cnte_14(3 downto 0), latch_in=>cnte_6_DUMMY, over_in=>cnte_7,

data_out1(3 downto 0)=>cnte_15(3 downto 0), data_out2(3 downto 0)=>cnte_16(3 downto 0), data_out3(3 downto 0)=>cnte_17(3 downto 0), data_out4(3 downto 0)=>cnte_18(3 downto 0), data_out5(3 downto 0)=>cnte_19(3 downto 0), data_out6(3 downto 0)=>cnte_20(3 downto 0), over_out=>over_out); end BEHAVIORAL;