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《EDA技术》习题

5 习 题

5-1 归纳利用Quartus II进行VHDL文本输入设计的流程：从文件输入一直到SignalTap II测试。P95~P115

答：1 建立工作库文件夹和编辑设计文件；2 创建工程；3 编译前设置；4 全程编译；5 时序仿真；6 引脚锁定；7 配置文件下载；8 打开SignalTap II编辑窗口；9 调入SignalTap II的待测信号；10 SignalTap II参数设置；11 SignalTap II参数设置文件存盘；12 带有SignalTap II测试信息的编译下载；13 启动SignalTap II进行采样与分析；14 SignalTap II的其他设置和控制方法。

5-2 由图5-40和图5-41，详细说明工程设计CNT10的硬件工作情况。P114~P115

答：图5-40给出工程设计CNT10的十进制计数工作情况；当计数CQ或CQI到9时,计数进位COUT输出正脉冲。图5-41给出工程设计CNT10的十进制计数和内部计数节点CQI计数线性递增的信号波形的工作情况。

5-3 如何为设计中的SignalTap II加入独立采样时钟?试给出完整的程序和对它的实测结果。P115

答：为SignalTap II提供独立时钟的方法是在顶层文件的实体中增加一个时钟输入端口，如语句:LOGC_CLK:IN STD_LOGIC;在此实体中不必对其功能和连接具体定义，而在SignalTap II的参数设置中则可以选择LOGC_CLK为采样时钟。

5-4 参考QuartusII的Help，详细说明Assignments菜单中Settings对话框的功能。 (1)说明其中的Timing Requirements&Qptions的功能、他用方法和检测途经。

Specifying Timing Requirements and Options (Classic Timing Analyzer)

You can specify timing requirements for Classic timing analysis that help you achieve the desired speed performance and other timing characteristics for the entire project, for specific design entities, or for individual clocks, nodes, and pins.

When you specify either project-wide or individual timing requirements, the Fitter optimizes the placement of logic in the device in order to meet your timing goals. You can use the Timing wizard or the Timing Analysis Settings

command to easily

specify all project-wide timing requirements, or you can use the Assignment Editor to assign individual clock or I/O timing requirements to specific entities, nodes, and pins, or to all valid nodes included in a wildcard or assignment group assignment. To specify project-wide timing requirements:

1. On the Assignments menu, click Settings.

2. In the Category list, select Timing Analysis Settings.

3. To specify project-wide tSU, tH, tCO, and/or tPD timing requirements, specify values

under Delay requirements.

4. To specify project-wide minimum delay requirements, specify options under

Minimum delay requirements.

5. Under Clock Settings, select Default required fmax.

6. In the Default required fmax box, type the value of the required fMAX and select a

time unit from the list.

7. If you want to specify options for cutting or reporting certain types of timing paths

globally, enabling recovery/removal analysis, enabling clock latency, and reporting unconstrained timing paths, follow these steps: 8. Click OK. To specify clock settings:

1. On the Assignments menu, click Settings.

2. In the Category list, select Timing Analysis Settings. 3. Under Clock Settings, click Individual Clocks. 4. Click New.

5. In the New Clock Settings dialog box, type a name for the new clock settings in the

Clock settings name box.

6. To assign the clock settings to a clock signal in the design, type a clock node name in

the Applies to node box, or click Browse... to select a node name using the Node Finder.

7. If you want to specify timing requirements for an absolute clock, follow these steps: 8. If you have already specified timing requirements for an absolute clock, and you want

to specify timing requirements for a derived clock, follow these steps: 9. In the New Clock Settings dialog box, click OK. 10. In the Individual Clocks dialog box, click OK. 11. In the Settings dialog box, click OK. To specify individual timing requirements:

1. On the Assignments menu, click Assignment Editor.

2. In the Category bar, select Timing to indicate the category of assignment you wish

to make.

3. In the spreadsheet, select the To cell and perform one of the following steps:

? Type a node name and/or wildcard that identifies the destination node(s) you want to assign.

? Double-click the To cell and click Node Finder to use the Node Finder to enter a node name.

? Double-click the To cell, click the arrow that appears on the right side of the cell, and click Select Assignment Group to enter an existing assignment group name.

4. To specify an assignment source, repeat step 3 to specify the source name in the

From cell.

5. In the spreadsheet, double-click the Assignment Name cell and select the timing

assignment you wish to make.

6. For assignments that require a value, double-click the Value cell and type or select

the appropriate assignment value.

To specify timing analysis reporting restrictions: 1. On the Assignments menu, click Settings.

2. In the Category list, double-click Timing Analysis Settings. 3. Click Timing Analyzer Reporting.

4. To specify the range of timing analysis information reported, specify one or more

options in the Timing Analyzer Reporting page. 5. Click OK.

(2)说明其中的Compilation Process的功能和使用方法。

Compilation Process Settings Page (Settings Dialog Box)

Allows you to direct the Compiler to use smart compilation, save synthesis results for the current design's top-level entity, disable the OpenCore Plus hardware evaluation feature, or export version-compatible database files. You can also control the amount of disk space used for compilation. Use Smart compilation:

Preserve fewer node names to save disk space: Run Assembler during compilation:

Save a node-level netlist of the entire design into a persistent source file: Export version-compatible database: Display entity name for node name:

Disable OpenCore Plus hardware evaluation feature:

(3)说明Analysis&Synthesis Setting的功能和使用方法，以及其中的Synthesis Netlist Optimization的功能和使用方法。

Analysis & Synthesis Settings Page (Settings Dialog Box)

Allows you to specify options for logic synthesis. Create debugging nodes for IP cores: More Settings: Other options: Message Level: Advanced:

Synthesis Netlist Optimizations Page (Settings Dialog Box)

Specifies the following options for optimizing netlists during synthesis: Perform WYSIWYG primitive resynthesis: Perform gate-level register retiming:

Allow register retiming to trade off Tsu/Tco with Fmax:

(4)说明FitterSettings中的DesignAssistant和Simulator功能，举例说明它们的使用方法。

Design Assistant Page (Settings Dialog Box)

Allows you to specify which rules you want the Design Assistant to apply when analyzing and generating messages for a design, and whether you want the Design Assistant to automatically analyze the design during a full compilation.

Run Design Assistant during compilation: Design Assistant configuration rule names: Advanced:

Simulator Settings Page

Allows you to specify settings that control simulation processing, such as the type of

simulation that should be performed, the time period covered by the simulation, the source of vector stimuli, and other options. Simulation also allows you to check setup and hold times, detect glitches, and check simulation coverage. You can also provide vector stimuli in a Vector Waveform File (.vwf), a Compressed Vector Waveform File (.cvwf), or a text-based Vector File (.vec). You can use Tcl commands and scripts to control simulation and to provide vector stimuli.

Simulation Mode: Simulation Input:

Automatically add pins to simulation output waveforms: Check outputs:

Waveform Comparison Settings: Setup and hold time violation detection: Glitch detection:

Simulation coverage reporting: Report Settings:

Overwrite simulation input file with simulation results:

Disable setup and hold time violation detection for input registers of bi-directional pins: More Settings:

5-5 概述Assignments菜单中Assignment Editor的功能，举例说明。

About the Assignment Editor

User Interface and Functionality: Customizing the User Interface: Pin Information: LogicLock Assignments:

Assignment Validation and Output: Integration with the Pin Planner:

5-6 用74148（8-3线八进位优先编码器）和与非门实现8421BCD优先编码器，用3(5)片74139（2线-4线译码器）组成一个5-24(4-16)线译码器。