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第3章 VHDL基础
3-1 如图所示
inputbuf3soutputenable3-2
程序： IF_THEN语句 LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 S
PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ;
ARCHITECTURE one OF mux21 IS BEGIN
PROCESS ( s0,s1,a,b,c,d ) BEGIN
IF s1=?0? AND s0=?0? THEN y<=a ; ELSIF s1=?0? AND s0=?1? THEN y<=b ; ELSIF s1=?1? AND s0=?0? THEN y<=c ; ELSIF s1=?1? AND s0=?1? THEN y<=d ; ELSE y<=NULL ; END IF ;
END PROCESS ; END ARCHITECTURE one ;
CASE 语句
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 IS
in0mux21outputin1sel
PORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ;
ARCHITECTURE two OF mux21 IS
SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN
s<=s1 & s0 ; PROCESS ( s ) BEGIN
CASE s IS
WHEN “00” => y<=a ; WHEN “01” => y<=b ;
WHEN “10” => y<=c ; WHEN “11” => y<=d ; WHEN OTHERS => NULL ;
END CASE ; END PROCESS ;
END ARCHITECTURE two ; 3-3 程序：
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY MUXK IS
PORT ( s0,s1 : IN STD_LOGIC ; a1,a2,a3 : IN STD_LOGIC ; outy : OUT STD_LOGIC ) ; END ENTITY MUXK ;
ARCHITECTURE double OF MUXK IS SIGNAL tmp : STD_LOGIC ; --内部连接线 SIGNAL u1_s, u1_a, u1_b, u1_y : STD_LOGIC ; SIGNAL u2_s, u2_a, u2_b, u2_y : STD_LOGIC ;
BEGIN
p_MUX21A_u1 : PROCESS ( u1_s, u1_a, u1_b, u1_y ) BEGIN
CASE u1_s IS
WHEN ?0? => u1_y<= u1_a ;
WHEN ?1? => u1_y<= u1_b ; WHEN OTHERS => NULL ; END CASE ;
END PROCESS p_ MUX21A_u1 ;
p_ MUX21A_u2 : PROCESS ( u2_s, u2_a, u2_b, u2_y ) BEGIN
CASE u2_s IS
WHEN ?0? => u2_y<= u2_a ;
WHEN ?1? => u2_y<= u2_b ; WHEN OTHERS => NULL ; END CASE ;
END PROCESS p_ MUX21A_u2 ; u1_s<= s0 ; u1_a<= a2 ; u1_b<= a3 ; tmp<= u1_y ;
u2_s<=s1 ; u2_a<= a1 ; u2_b<= tmp; outy <= u2_y ;
END ARCHITECTURE double ; 3-4 程序：
（1）1位半减器
被减数减数高位低位x0011
y0101s_outdiff01000110
s_out= x · ydiff= x · y + x · yxnotands_outxor(2)diff
y1位半减器的设计选用（2）图，两种表达方式：
一、 LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY h_suber IS
PORT ( x,y : IN STD_LOGIC ;
s_out ,diff : OUT STD_LOGIC ) ; END ENTITY h_suber ;
ARCHITECTURE fhd1 OF h_suber IS
BEGIN
diff<=x XOR y ; s_out<= ( NOT a ) AND b ; END ARCHITECTURE fhd1 ; 二、 LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY h_suber IS
PORT ( x,y : IN STD_LOGIC ;
s_out ,diff : OUT STD_LOGIC ) ; END ENTITY h_suber ;
ARCHITECTURE fhd1 OF h_suber IS
SIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; BEGIN s<= x & y ; PROCESS ( s ) BEGIN
CASE s IS
WHEN “00” => s_out <=?0? ; diff<=?0? ; WHEN “01” => s_out <=?1? ; diff<=?1? ;
WHEN “10” => s_out <=?0? ; diff<=?1? ; WHEN “11” => s_out <=?0? ; diff<=?0? ; WHEN OTHERS => NULL ;
END CASE ; END PROCESS ;
END ARCHITECTURE fhd1 ; 或门逻辑描述： LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY or IS
PORT ( a,b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END ENTITY or ;
ARCHITECTURE one OF or IS BEGIN c<= a OR b ;
END ARCHITECTURE one ; 1位全减器： LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ; ENTITY f_suber IS
PORT ( x,y,sub_in : IN STD_LOGIC ; sub_out ,diffr : OUT STD_LOGIC ) ; END ENTITY f_suber ;
ARCHITECTURE fhd1 OF f_suber IS COMPONENT h_suber IS PORT ( x,y : IN STD_LOGIC ;
s_out ,diff : OUT STD_LOGIC ) ; END COMPONENT h_suber ; COMPONENT or IS
PORT ( a,b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END COMPONENT or ; SIGNAL d,e,f : STD_LOGIC ; BEGIN
u1 : h_suber PORT MAP ( x=>x, y=>y, diff=>d, s_out=>e ) ; u2 : h_suber PORT MAP ( x=>d, y=>sub_in, diff=>diffr, s_out=>f ) ; u3 : or PORT MAP ( a=>f, b=>e, c=>sub_out ) ; END ARCHITECTURE fhd1 ;
（2）8位减法器：