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HEFEI UNIVERSITY

课程设计报告

基于VHDL语言数字钟的设计 I

摘 要

本设计主要研究基于VHDL的语音数字钟的设计，该数字钟具有年、月、日、时、分、秒计数显示功能，以24小时循环计数；具有校对功能、整点报时以及清零、使能功能。

本设计主要是在介绍了EDA及VHDL一些相关基本知识的基础上，进一步采用EDA技术，以硬件描述语言VHDL为系统逻辑描述手段设计文件，在Max+plusII工具软件环境下，采用自顶向下的设计方法，由各个基本模块共同构建了一个多功能语音数字钟，最后通过仿真出时序图实现预定功能。其中，重点叙述了数字钟的设计原理和分模块实现的方法，详细介绍了各模块的设计程序并给出了各模块的波形仿真图及分析，最后通过在Max+plusII上进行时序仿真，调试运行，在硬件测试后，验证了所设计的系统达到了预先设计目标。

通过这次的设计更进一步地增强了实验的动手能力，对数字钟的工作原理及EDA技术也有了更加透彻的理解。

关键词：VHDL EDA 数字钟 仿真图

II

The Design of a Voice Digital Clock Based on VHDL

Abstract

The design for a multi-functional digital clock, with a year, month, day, hours, minutes and seconds count display to a 24-hour cycle count; have proof functions and the whole point timekeeping function.

The design is mainly the introduction of the EDA and some related basic knowledge of VHDL, based on the further use of EDA technology,

hardware-description language VHDL description logic means for the system design documents, in MaxplusII tools environment, a top-down design, by the various modules together build a voice digital clock. Finally, a timing diagram of the simulation to achieve the intended function. Describes the key design principles and digital clock sub-module approach. Finally,by Max + plusII on timing simulation, debugging and running, by the hardware testing, the two systems designed are verified to realize the advanced design goal.

Through this experimental design further enhances the ability of the digital clock works and EDA technology has a more thorough understanding.

Keywords: VHDL EDA digital clock Simulation diagram

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