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光纤通信系统5B6B码编码的设计与仿真

中文摘要

在现代数字通信系统中，线路编码因为他在数字通信光纤中具有的优点和长处而成为一种趋势，因此被广泛使用。在数字光纤通信系统，数字光纤通信传输线的字符编码转换和数字信号传送的特征组合起来就形成了电气信号通过电机的传输。改变数字流 “0”、“1”位的码字的平衡，以避免“0”的长连续和“1”的长连现象出现在数据流中。在光纤通信线路的数字编码系统，可用于多种模式，常用模型之一是mBnB模型。

本文通过介绍5B6B编码原理，设计编码方案，以及硬件描述语言VHDL和Altera公司的Quartus II 软件的使用，完成了5B6B码的编码与仿真。5B6B具有显着较低的误码扩散系数，相同符号的最大连续码元总和少，时间信息是丰富的，有一个简单的完备的错误监测和同步码组的方法。

关键词：光纤数字通信系统 ；5B6B编码 ；VHDL ；Quartus II

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5B6B Coding Optical Fiber Communication System Design And

Simulation

ABSTRACT

In modern digital communication systems, line coding is a trend, due to their own advantages and strengths, digital fiber optic communication has been widely used. In the digital fiber optic communication systems, electrical signals coming from the electrical machine transmission is by the end of optical fiber communication lines with the digital transmission format conversion features together. Changing the balance of the digital stream, \ \and the length \phenomenon appears in the data stream. In the digital fiber-optic communication line coding system can be used for many reasons, one of the commonly used model is mBnB pattern.

This paper describes the 5B6B coding theory, design coding scheme and use altera company's hardware description language VHDL and Quartus II software system development, to achieve a 5B6B coding simulation. 5B6B advantage is significantly lower coefficient of error diffusion, achieved the maximum same symbol codes sum little ,timing information-rich, there is a simple method for error monitoring and sophisticated synchronization code groups.

KEY WORDS : Digital Optical Fiber Communication System ; 5B6B coding ;

VHDL ; Quartus II

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目 录

第一章 绪论 ..................................................................................................................................... 1

1.1 引言 .................................................................................................................................... 1 1.2 Quartus II 软件介绍 ..................................................................................................... 1 1.3 VHDL语言 ......................................................................................................................... 3

1.3.1 背景简介 ................................................................................................................. 3 1.3.2 VHDL主要特点 ................................................................................................... 4 1.3.3 VHDL主要优势 ................................................................................................... 5

第二章 FPGA系统开发过程 ......................................................................................................... 6

2.1 电路设计 ............................................................................................................................ 6 2.2 设计输入 ............................................................................................................................ 6 2.3功能仿真 ............................................................................................................................. 6 2.4综合优化 ............................................................................................................................. 7 2.5综合后仿真 ......................................................................................................................... 7 2.6实现与布局布线 ................................................................................................................. 7 3.1 5B6B编码 .......................................................................................................................... 8

3.1.1 5B6B编码原理 ...................................................................................................... 8 3.1.2 5B6B码表设计 .................................................................................................... 9 3.2 5B6B编码模块设计 ........................................................................................................ 11

3.2.1 编码器的工作原理 ............................................................................................... 11 3.2.2 编码电路模块划分 ............................................................................................... 11 3.3 系统各个模块的设计 ...................................................................................................... 12

3.3.1 时钟控制模块的设计 ........................................................................................... 12 3.3.2串并转换模块的设计 ............................................................................................ 12 3.3.3 缓存电路的设计 ................................................................................................... 12 3.3.4 并串转换模块的设计 ........................................................................................... 13 3.3.5 系统的顶层设计 ................................................................................................... 13 3.4 系统各个模块的仿真 ...................................................................................................... 14

3.4.1分频器的仿真 ........................................................................................................ 14 3.4.2 串并转换模块的仿真 ........................................................................................... 14 3.4.3 存储器模块的仿真 ............................................................................................... 14 3.4.4 并串转换模块的仿真 ........................................................................................... 15 3.4.5 完整电路仿真 ....................................................................................................... 16

第四章 总结 ................................................................................................................................... 17 参考文献......................................................................................................................................... 18 致 谢......................................................................................................................................... 19 图表目录......................................................................................................................................... 20

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