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Design and Implementation of Digital Cymometer Based on CPLD

Abstract

With the adoption of the top-down design method and AT89C51 SCMC (Single Chip Mico Computer) as the master control component of the system ,the circuit test signalcontrolling ,data operation processing ,keyboard scanning ,and nixie tube

display as well were completed by the digital cymometer.A

CPLD ,EPM7128SLC84-15 ,programmed by VHDL ,realized various sequence control and count functions .The system is characterized by impact structure ,high

reliability ,high precision ,and wide frequency-test-range .

Keywords digital cymometer，complex programmable logic device，SCMC，EDA

technology

1 Introduction

The system core called SCMC (Single Chip Mico Computer) emerges constantly despite the unceasing development of electronic and computer technologies.The frequency measurement or cycle measurement is usually utilized for testing signals

that use frequency as a parameter. When the tested frequency is relatively

high ,relatively high precision can be available with frequency measurement . When the tested frequency isrelatively low ,relatively high precision can be a vailable with cycle measurement . However , neither of them can ensure the measurement precision in the whole frequency range ,when the range of tested frequency is comparatively

wide .

This digital Cymometer utilizes the advanced EDA technology and top-down design method . Thus ,the Cynometer implements the equal precision measurement of

the signal frequency range of 0.1 Hz～50MHz

by AT89C51 SCMC and CPLD，and also measures pulse width and duty ratio . Because of the convenience of CPLD programming ,quick speed , high integration ,

and low price , the system research circle is extremely

shortened and the product ratio of performance versus price is improved . The CPLD chip employs the popular VHDL and achieves all the program design and Download on the MAX+PlusII software platform . The control portion of SCMC ,programmed by assemble language precisely sets time , exactly controls startup and closedown of frequency-test count strobe ,which further ensures measurement precision . System

theory and software & hardware design are introduced below .

2 Equal precision measurement theory

In CPLD ,top-level circuit structure realized by VHDL is shown in figure 1 ,where CONTROL1 is control module of frequency-est ,CONTROL2 is control

module of pulse-width-test and duty ratio,CHOICE is choice module of

self-djustment and measurement ;COUNT is count module of datum frequency and frequency-test . Under the control of SCMC ,the CPLD accomplishes frequency-test

in the following steps :

(a) Plus pulse signal is added at CLR , thereby completing the initialization of testing circuit state (when frequency is tested ,CS ,AS is low ,ED2 is irrelevant ) .

(b) When strobe signal STROBE is set high ,timing starts . Meanwhile ,rising edge of pulse-test signal Fx ,which is selected by CHOICE module , initiates frequency-test control module CONTROL1 , which makes two sets of 32-bit counter within COUNT take count of datum frequency signal Fs and signal-test Fx synchro no

usly .

(c) STROBE is set low when stro be timing ends . COUNT stops counting once

rising edge of next pulse of signal-test advents .

(d) After count finishes ,ED1 outputs low level to apply for interrupt from

SCMC. In the Interrupt Service Routine ,SCMC reads count value of datum frequency signal and signal-test in COUNT from port P0 and P2 of SCMC for four times , through encoding address line SS1 and SS0 . If the count value of signal-test is

Nx ,datum frequency’s is Ns ,then Fx=( Fs/ N s) N x .

Fig . 1 Frequency measurement top-level module

3 Design of system hardware circuit

The block diagram of system hardware circuit is shown in f igure 2 .

There is a 4 kB Flash Memory in A T89C51 SCMC into which all control program can be stored . SCMC writes the result tested from CPLD each time into RAM ,and t hen sends it in decimal into eight-bit nixie tube display circuit to display after operation processing . Keyboard control command is written into SCMC via a 74LS165 ,Parallel in/ Serial Output Shift Registers . SCMC utilizes one 12MHz crystal whose oscilla-tion pulse is served as self-adjustment input of CPLD at the same time . Signal-test is inputted to CPLD via wide band amplify and Schmitt circuit

shape . 50MHz active crystal module is used for datum frequency input .

4 VHDL program design

CPLD software program is achieved by VHDL . A portion of top-level module

program is as follow :

LIBRARY IEEE ;

USE IEEE. STD_LOGIC_1164 . ALL ;

USE IEEE. STD_LOGIC_UNSIGNED . ALL ;

ENTITY FREQUENCY8 IS

PORT ( SS0 ,SS1 ,FS ,FX ,FC ,CLR ,AS ,STROBE ,CS : IN STD_LOGIC ;

ED1 , ED2 :OUT STD_LOGIC ;

B :OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ) ;

END FREQUENCY8 ;

ARCHITECTURE RTL OF FREQUENCY8 IS

SIGNAL FX0 ,CLKX ,CLKS ,CLE ,SSL1 : STD_LOGIC ;

……

COMPONENT COUNT

PORT ( FX1 ,FS1 ,CLR ,SS0 ,SS1 : IN STD_LOGIC ; B :OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ) ;

END COMPONENT ;

BEGIN

U1 :CHOICE PORT MAP ( FX => FX ,FC => FC ,AS =>AS ,

FOUT =>FX0) ;

U2 :CONTROL1 PORT MAP( FX1=>FX0 , STROBE =>STROBE , CLR=>CLR , FS=>FS ,CS =>CS ,SSL=>SSL1 ,CLK1=>CLKX ,

CLK2 =>CLKS ,CLRC =>CLE ,ED1 => ED1) ;

U3 :CONTROL2 PORT MAP( FIN=>FX0 ,STROBE => STROBE ,

CLR=>CLR ,SSL=>SSL 1 ,ED2=>ED2) ;

U4 :COUNT PORT MAP(FX1=>CLKX ,FS1=>CLKS ,CLR=>CLE ,

SS0 = > SS0 ,SS1 = > SS1 ,B = > B) ;

END RTL ;

Figure 3 is the emulation waveform diagram when signal-test Fx=10MHz and

Fs=50MHz .

Fig . 2 Emulation waveform diagram

5 Frequency-test precision analysis

From the frequency-test formula : Fx = (Fs/ Ns) Nx . Suppose that frequency-test is Fx ,its true value is Fxe ,and standard frequency is Fs. In one measurement ,because

Fx count startup and closedown time are both triggered by the signal’s rising edge ,count Nx of Fx has no error in one strobe time T ,while count Ns has error of

one pulse at most , that is

| Δet | ≤1 , we can derived Fxe =( Fs/(N s +△et) ) Nx from

Fx/Nx = Fs/Ns and Fxe/Nx = Fs/(Ns +Δet ) . According to relative error formula ΔFxe/ Fxe =| Fxe -Fx | /Fxe ,we have ΔFxe/ Fxe = |Δet| /Ns. Then , since | Δet | ≤1 ,

we obtain | Δet | / N s ≤1/ Ns ,Ns = TFs.

Accordingly we reach the conclusion that relative measurement error has no relation to frequency-test ,measurement error which can be reduced and measurement precision improved via augmenting strobe time T or enhancing Fs. The measurement precision of frequency-test system remains constant in the entire frequency range in case that strobe time and general frequency measurement strobe time is uniform and

signal-test frequency is dissimilar .

The range of this system frequency-test is set as from 0.1Hz to 50MHz . Strobe time is set to two grades :1s and 10s . The strobe can test and obtain signal once every 10s when frequency-test is 0.1Hz .50MHz upper limit frequency setting depends on such factors as internal counter digit of CPLD , CPLD clock ,nixie tube digit ,and so on . In 10s strobe time ,50MHz datum frequency can count 500MHz pulse(only 29 bits binary number required) ,while 400MHz can be counted in theory as the 32-bit of