内容发布更新时间 : 2024/12/24 11:38:37星期一 下面是文章的全部内容请认真阅读。
end entity CNT10; architecture art of CNT10 is signal cqi:integer range 0 to 15; begin
process(clk,clr,ena) is begin
if clr='1' then cqi<=0; elsif clk'event and clk='1' then if ena='1' then
if cqi<9 then cqi<=cqi+1;
else cqi<=0;end if; end if; end if; end process; cq<=cqi;
end architecture art;
FRE_DIVIDE library ieee; use ieee.std_logic_1164.all; entity FRE_DIVIDE is port(clk_1M:in std_logic; clk_1K,clk_1MZ:out std_logic); end entity FRE_DIVIDE; architecture art of FRE_DIVIDE is signal cout1,cout2:integer; signal K,MZ:std_logic; begin
process(clk_1M) is begin clk_1K<=K; clk_1MZ<=MZ;
if (clk_1M'event and clk_1M='1') then
if cout1<999999 then cout1<=cout1+1;MZ<='0';
else cout1<=0;MZ<='1';end if;
if cout2<9999 then cout2<=cout2+1;K<='0'; else cout2<=0;K<='1';end if; end if; end process; end architecture art; REG32B library ieee;
use ieee.std_logic_1164.all; entity REG32B is port(load:in std_logic;
din:in std_logic_vector(31 downto 0); dout:out std_logic_vector(31 downto 0)); end entity REG32B;
architecture art of REG32B is begin
process(load,din)is begin
if load'event and load='1' then dout<=din; end if; end process; end architecture art;
SEG7-DEC Library ieee;
Use ieee.std_logic_1164.all; Entity SEG7_DEC is
Port(bcd:in std_logic_vector(3 downto 0); y:out std_logic_vector(6 downto 0)); End entity SEG7_DEC; Architecture rt1 of SEG7_DEC is Begin Process(bcd) is
Begin Case bcd is
When \ When \ When \ When \ When \ When \ When \ When \ When \ When \ When others=>y<=\ End case; End process; End architecture rt1;
TESTCT1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity testctl is port(clk:in std_logic; tsten,clr_cnt,load:out std_logic); end entity testctl; architecture art of testctl is signal div2clk:std_logic; begin process(clk)is begin
if clk'event and clk='1' then div2clk<=not div2clk; end if; end process; process(clk,div2clk)is begin
if clk='0'and div2clk='0' then clr_cnt<='1'; else clr_cnt<='0'; end if; end process;
load<=not div2clk;tsten<=div2clk; end architecture art; 2、
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