内容发布更新时间 : 2024/5/10 1:01:34星期一 下面是文章的全部内容请认真阅读。
集成电路课程设计
reg cos_ena; reg sawtooth_ena; reg triangle_ena;
reg [8:0]data_out;
wire [8:0] sine_d; wire [8:0] cosine_d; wire [8:0] sawtooth_d; wire [8:0] triangle_d; wire [8:0] rom_ad;
assign rom_ad = ADD_B;
always@(posedge clk or negedge rst) begin
if(!rst) begin ADD_A <= 9'd0; end else case(we)
1'b1 : ADD_A <= data; 1'b0 : ADD_A <= 9'd0; default: ADD_A <= 9'd0; endcase end
always@(posedge clk or negedge rst)
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集成电路课程设计
begin
if(!rst) begin
ADD_B <= 9'b0; sin_ena<=1'b0; cos_ena<=1'b0; sawtooth_ena <= 1'b0; triangle_ena <= 1'b0; end else begin
case(choose_wave) 2'b00:begin
sin_ena <= 1'b1; cos_ena <= 1'b0; sawtooth_ena <= 1'b0; triangle_ena <= 1'b0;
if(ADD_B > 256) ADD_B <= 0; else ADD_B <= ADD_A + ADD_B; end 2'b01:begin
cos_ena <= 1'b1; sin_ena <= 1'b0; sawtooth_ena <= 1'b0; triangle_ena <= 1'b0;
if(ADD_B > 256) ADD_B <= 0; else ADD_B <= ADD_A + ADD_B; end 2'b10:begin
sin_ena <= 1'b0;
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集成电路课程设计
cos_ena <= 1'b0; sawtooth_ena <= 1'b1; triangle_ena <= 1'b0;
if(ADD_B > 256) ADD_B <= 0; else ADD_B <= ADD_A + ADD_B; end end end
always@(posedge clk)
2'b11:begin
sin_ena <= 1'b0; cos_ena <= 1'b0; sawtooth_ena <= 1'b0; triangle_ena <= 1'b1;
if(ADD_B > 256) ADD_B <= 0; else ADD_B <= ADD_A + ADD_B; end default:begin
ADD_B <= 9'b0; sin_ena <= 1'b0; cos_ena <= 1'b0; sawtooth_ena <= 1'b0; triangle_ena <= 1'b0; end endcase - 23 -
集成电路课程设计
begin
case(choose_wave) 2'b00:begin
data_out <= sine_d; end 2'b01:begin
data_out <= cosine_d; end 2'b10:begin
data_out <= sawtooth_d; end 2'b11:begin
data_out <= triangle_d; end default:begin
data_out <= 9'b0; end endcase end
rom_sin rom_sin1(
.address(rom_ad), .clock(clk), .ena(sin_ena), .wr_data(sine_d) );
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集成电路课程设计
rom_cos rom_cos1(
.address(rom_ad), .clock(clk), .ena(cos_ena), .wr_data(cosine_d) ); rom_triangle rom_triangle1(
.address(rom_ad), .clock(clk), .ena(triangle_ena), .wr_data(triangle_d) );
rom_sawtooth rom_sawtooth1( .address(rom_ad), .clock(clk), .ena(sawtooth_ena), .wr_data(sawtooth_d) ); endmodule
附录2:sin函数查找表
module rom_sin(
address, clock, wr_data,
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