基于Verilog实现的DDS任意波形发生器 下载本文

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集成电路课程设计

ena ); input [8:0]address; input clock; input ena; output [8:0]wr_data; reg [8:0]wr_data;

always@(posedge clock) if(ena) begin

case(address)

0 : begin wr_data <=0; end

1 : begin wr_data <=6; end 2 : begin wr_data <=13; end 3 : begin wr_data <=19; end 4 : begin wr_data <=25; end 5 : begin wr_data <=31; end 6 : begin wr_data <=37; end 7 : begin wr_data <=44; end 8 : begin wr_data <=50; end 9 : begin wr_data <=56; end 10 : begin wr_data <=62; end 11 : begin wr_data <=68; end 12 : begin wr_data <=74; end 13 : begin wr_data <=80; end 14 : begin wr_data <=86; end 15 : begin wr_data <=92; end 16 : begin wr_data <=98; end

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集成电路课程设计

17 : begin wr_data <=103; end 18 : begin wr_data <=109; end 19 : begin wr_data <=115; end 20 : begin wr_data <=120; end 21 : begin wr_data <=126; end 22 : begin wr_data <=131; end 23 : begin 24 : begin 25 : begin 26 : begin 27 : begin 28 : begin 29 : begin 30 : begin 31 : begin 32 : begin 33 : begin 34 : begin 35 : begin 36 : begin 37 : begin 38 : begin 39 : begin 40 : begin 41 : begin 42 : begin 43 : begin 44 : begin 45 : begin 46 : begin wr_data <=136; wr_data <=142; wr_data <=147; wr_data <=152; wr_data <=157; wr_data <=162; wr_data <=166; wr_data <=171; wr_data <=176; wr_data <=180; wr_data <=185; wr_data <=189; wr_data <=193; wr_data <=197; wr_data <=201; wr_data <=205; wr_data <=208; wr_data <=212; wr_data <=215; wr_data <=219; wr_data <=222; wr_data <=225; wr_data <=228; wr_data <=230; end end end end end end end end end end end end end end end end end end end end end end end end

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集成电路课程设计

47 : begin wr_data <=233; end 48 : begin wr_data <=236; end 49 : begin wr_data <=238; end 50 : begin wr_data <=240; end 51 : begin wr_data <=242; end 52 : begin wr_data <=244; end 53 : begin 54 : begin 55 : begin 56 : begin 57 : begin 58 : begin 59 : begin 60 : begin 61 : begin 62 : begin 63 : begin 64 : begin 65 : begin 66 : begin 67 : begin 68 : begin 69 : begin 70 : begin 71 : begin 72 : begin 73 : begin 74 : begin 75 : begin 76 : begin wr_data <=246; wr_data <=247; wr_data <=249; wr_data <=250; wr_data <=251; wr_data <=252; wr_data <=253; wr_data <=254; wr_data <=254; wr_data <=255; wr_data <=255; wr_data <=255; wr_data <=255; wr_data <=255; wr_data <=254; wr_data <=254; wr_data <=253; wr_data <=252; wr_data <=251; wr_data <=250; wr_data <=249; wr_data <=247; wr_data <=246; wr_data <=244; end end end end end end end end end end end end end end end end end end end end end end end end

- 28 -

集成电路课程设计

77 : begin wr_data <=242; end 78 : begin wr_data <=240; end 79 : begin wr_data <=238; end 80 : begin wr_data <=236; end 81 : begin wr_data <=233; end 82 : begin wr_data <=231; end 83 : begin wr_data <=228; end 84 : begin wr_data <=225; end 85 : begin wr_data <=222; end 86 : begin wr_data <=219; end 87 : begin wr_data <=216; end 88 : begin wr_data <=212; end 89 : begin wr_data <=209; end 90 : begin wr_data <=205; end 91 : begin wr_data <=201; end 92 : begin wr_data <=197; end 93 : begin wr_data <=193; end 94 : begin wr_data <=189; end 95 : begin wr_data <=185; end 96 : begin wr_data <=181; end 97 : begin wr_data <=176; end 98 : begin wr_data <=171; end 99 : begin wr_data <=167; end 100 : begin wr_data <=162; end 101 : begin wr_data <=157; end 102 : begin wr_data <=152; end 103 : begin wr_data <=147; end 104 : begin wr_data <=142; end 105 : begin wr_data <=137; end 106 : begin wr_data <=131; end

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集成电路课程设计

107 : begin wr_data <=126; end 108 : begin wr_data <=121; end 109 : begin wr_data <=115; end 110 : begin wr_data <=109; end 111 : begin wr_data <=104; end 112 : begin wr_data <=98; end 113 : begin 114 : begin 115 : begin 116 : begin 117 : begin 118 : begin 119 : begin 120 : begin 121 : begin 122 : begin 123 : begin 124 : begin 125 : begin 126 : begin 127 : begin 128 : begin 129 : begin 130 : begin 131 : begin 132 : begin 133 : begin 134 : begin 135 : begin 136 : begin wr_data <=92; end wr_data <=86; end wr_data <=80; end wr_data <=74; end wr_data <=68; end wr_data <=62; end wr_data <=56; end wr_data <=50; end wr_data <=44; end wr_data <=38; end wr_data <=32; end wr_data <=25; end wr_data <=19; end wr_data <=13; end wr_data <=7; end wr_data <=0; end wr_data <=-5; end wr_data <=-11; end wr_data <=-17; end wr_data <=-24; end wr_data <=-30; end wr_data <=-36; end wr_data <=-42; end wr_data <=-48; end

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