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totalmoney:=0; castmoney:=0; restmoney:=0; Tnumber <=\ Minput<=\ Toutnum<=\ Changeout<=\ else next_state := givechange; end if; end case ; end if; end if; end process; end behave; 2.2k分频模块div_2k.vhd --------------------------------------------- --File Name : div_2k.vhd --Description : Help to achieve the function of auto ticket selling --Limition : None --System : Vhdl_9.0 --Soft : Quartus2_9.0 --Author : ChenDawen --Revision : Version 1.0 ，2012-10-31 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; entity div_2k is port(clk_in:in std_logic; clk_out:out std_logic); end div_2k; architecture a of div_2k is signal temp:integer range 0 to 1999; begin p1:process(clk_in) begin if clk_in'event and clk_in='1' then if temp=1999 then temp<=0; else temp<=temp+1; end if; end if; end process p1; p2:process(temp) begin if temp=1999 then clk_out<='1'; else clk_out<='0'; end if; end process p2; end a; 3. 500k分频模块div_500k.vhd --------------------------------------------- --File Name : div_500k.vhd --Description : Help to achieve the function of auto ticket selling --Limition : None --System : Vhdl_9.0 --Soft : Quartus2_9.0 --Author : ChenDawen --Revision : Version 1.0 ，2012-10-31 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; entity div_500k is --防抖信号分频为100Hz port(clk_in2:in std_logic; clk_out2:out std_logic);