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合肥工业大学宣城校区 微电子科学与工程 Verilog数字系统设计
79、分频系数为7，占空比为1:6的奇数分频器
module clk_div7(clk,clk7); input clk; output div7; reg div7; reg[2:0] cnt;
always@(posedge clk) begin
if(cnt == 3'b110)
begin cnt <= 0; div7 <= 1; end else
begin cnt <= cnt + 1'b1; div7 <= 0; end end endmodule
80、带使能端和复位端的时钟同步8位寄存器组逻辑
module register8(ena,clk,data,rst,out); input ena,clk,rst; input[7:0] data; output[7:0] out; reg[7:0] out;
always@(posedge clk) if(!rst)
out <= 0; else if(ena)
out <= data; endmodule
81、自触发always块
//使用阻塞赋值，不能自行触发的振荡器； module osc1(clk); output clk; reg clk;
initial #10 clk = 0;
always@(clk) #10 clk = ~clk; //该语句等价于:
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合肥工业大学宣城校区 微电子科学与工程 Verilog数字系统设计
// always; // begin
// @(clk) ;
// #10 clk = ~clk; // end endmodule
//使用非阻塞赋值，自行触发的振荡器； module osc1(clk); output clk; reg clk;
initial #10 clk = 0;
always@(clk) #10 clk <= ~clk; //该语句等价于: // always; // begin
// @(clk) ;
// #10 clk <= ~clk; // end endmodule
82、1001序列信号检测器
//一段式风格
module fsm1(clk,reset,data_in,data_out); input clk,reset,data_in; output data_out; reg data_out; reg[4:0] state; parameter //
start_s = 5'b10000, first_s = 5'b01000, second_s = 5'b01000, third_s = 5'b00010, last_s = 5'b00001; always@(posedge clk) if(!reset) begin
state <= start_s; data_out <= 0; end else
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合肥工业大学宣城校区 微电子科学与工程 Verilog数字系统设计
case(state) start_s: begin
data_out <= 0;
if(data_in) state <= first_s; else state <= start_s; end first_s: // begin
data_out <= 0; if(data_in==0)
state<= secend_s; else state <= first_s; end second: // begin
data_out <= 0; if(data_in == 0)
state <= third_s; else state <= first_s; end third_s:// begin
data_out <= 0;
if(data_in == 0) state <= start_s; else state <= last_s; end last_s: begin
data_out <= 1;
if(data_in == 0) state<= start_s; else state<= first_s; end
default: begin state<= start_s;
data_out<= 0; end endcase endmodule
//两段式风格
module fsm2(clk,reset,data_in,data_out); input clk,reset,data_in; output data_out; reg data_out; reg[4:0] state;
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合肥工业大学宣城校区 微电子科学与工程 Verilog数字系统设计
parameter //
start_s = 5'b10000, first_s = 5'b01000, second_s = 5'b01000, third_s = 5'b00010, last_s = 5'b00001;
//assign data_out= (state==last_s)?1：0； assign data_out = last_s[0]; always@(posedge clk) if(!reset)
stste <= start_s; else
case(state) start_s: begin
if(data_in)
state <= first_s; else
state <= start_s; end first_s: //
if(data_in==0)
state<= secend_s; else
state <= first_s; second: //
if(data_in == 0) state <= third_s; else
state <= first_s; third_s://
if(data_in == 0) state <= start_s; else
state <= last_s; last_s: //
if(data_in == 0) state<= start_s; else
state<= first_s; default:
state<= start_s; endcase endmodule
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合肥工业大学宣城校区 微电子科学与工程 Verilog数字系统设计
//三段式风格
module fsm2(clk,reset,data_in,data_out); input clk,reset,data_in; output data_out; reg data_out;
reg[4:0] state, next_state; parameter //
start_s = 5'b10000, first_s = 5'b01000, second_s= 5'b01000, third_s = 5'b00010, last_s = 5'b00001;
//每一个时钟沿产生一次可能的状态变化-always@(posedge clk) if(!reset)
state <= start_s; else
state <= nextstate;
//-------------------------------------------------- //--产生下一个状态的组合逻辑------------ always@(state or data_in) case(state) start_s:
if(data_in)
nextstate = first_s; else
nextstate = start_s; first_s: //
if(data_in==0)
nextstate<= secend_s; else
nextstate <= first_s; second: //
if(data_in == 0)
nextstate <= third_s; else
next state <= first_s; third_s://
if(data_in == 0)
nextstate <= start_s; else
nextstate <= last_s; last_s: //
if(data_in == 0)
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