内容发布更新时间 : 2024/11/15 4:48:18星期一 下面是文章的全部内容请认真阅读。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADC0809 IS
PORT(D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --来自0809转换好的8位数据 CLK: IN STD_LOGIC; --状态机工作时钟 RST: IN STD_LOGIC; --系统复位控制
EOC: IN STD_LOGIC; --转换状态指示，低电平表示正在转换 ALE:OUT STD_LOGIC; --8个模拟信号通道地址锁存信号 START:OUT STD_LOGIC; --转换开始信号
OE:OUT STD_LOGIC; --数据输出三态控制信号 ADDA:OUT STD_LOGIC; --信号通道最低位控制信号 --LOCK_T:OUT STD_LOGIC; --观察数据锁存时钟
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8位数据输出 END ADC0809;
ARCHITECTURE behav OF ADC0809 IS
TYPE states IS(s0,s1,s2,s3,s4); --定义各状态子类型 SIGNAL cs,next_state: states:=s0;
SIGNAL REGL: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK: STD_LOGIC;--转换后数据输出锁存时钟信号
attribute keep : boolean;
attribute keep of LOCK : signal is true; BEGIN
ADDA<='0';--当ADDA<='0'，选择模拟信号通道IN0；当ADDA<='1'，则选择通道IN1 --LOCK_T<=LOCK;
COM: PROCESS(cs,EOC) BEGIN --规定各状态转换方式 CASE cs IS
WHEN s0=> ALE<='0';START<='0';OE<='0';LOCK<='0';next_state<=s1; --0809初始化 WHEN s1=> ALE<='1';START<='1';OE<='0';LOCK<='0';next_state<=s2 ;--启动采样 WHEN s2=> ALE<='0';START<='0';OE<='0';LOCK<='0';
IF(EOC='1') THEN next_state<=s3; --EOC=1表明转换结束 ELSE next_state<=s2; END IF; --转换未结束，继续等待
WHEN s3=> ALE<='0';START<='0';OE<='1';LOCK<='0';next_state<=s4;--开启OE，输出转换好的数据
WHEN s4=> ALE<='0';START<='0';OE<='1';LOCK<='1';next_state<=s0; WHEN OTHERS=> ALE<='0';START<='0';OE<='0';LOCK<='0';next_state<=s0; END CASE; END PROCESS COM;
REG:PROCESS(CLK,RST) BEGIN
IF(RST='1') THEN cs<=s0;
ELSIF(CLK'EVENT AND CLK='1') THEN cs<=next_state;END IF; END PROCESS REG; --由信号cs将当前状态值带出此进程：REG
LATCH1: PROCESS(LOCK) --此进程中，在LOCK的上升沿，将转换好的数据锁入 BEGIN
IF LOCK='1' AND LOCK'EVENT THEN REGL<=D;END IF; END PROCESS LATCH1; Q<=REGL; END behav;
10-5 给出例10-3的完整程序。
--10-5 给出例10-3(COM1产生次态和COM2输出命令的3进程状态机)完整程序 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADC0809 IS
PORT(D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --来自0809转换好的8位数据 CLK: IN STD_LOGIC; --状态机工作时钟 RST: IN STD_LOGIC; --系统复位控制
EOC: IN STD_LOGIC; --转换状态指示，低电平表示正在转换 ALE:OUT STD_LOGIC; --8个模拟信号通道地址锁存信号 START:OUT STD_LOGIC; --转换开始信号
OE:OUT STD_LOGIC; --数据输出三态控制信号 ADDA:OUT STD_LOGIC; --信号通道最低位控制信号 LOCK_T:OUT STD_LOGIC; --观察数据锁存时钟
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8位数据输出 END ADC0809;
ARCHITECTURE behav OF ADC0809 IS
TYPE states IS(st0,st1,St2,st3,st4); --定义各状态子类型 SIGNAL cs,next_state: states:=st0; SIGNAL REGL: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK: STD_LOGIC;--转换后数据输出锁存时钟信号 BEGIN
ADDA<='1';--当ADDA<='0'，选择模拟信号通道IN0；当ADDA<='1'，则选择通道IN1 LOCK_T<=LOCK;
COM1: PROCESS(cs,EOC) BEGIN --译码产生次态 CASE cs IS
WHEN st0=> next_state<=st1; --0809初始化 WHEN st1=> next_state<=st2 ;--启动采样
WHEN st2=> IF(EOC='1') THEN next_state<=st3;--EOC=1表明转换结束 ELSE next_state<=st2; END IF; --转换未结束，继续等待 WHEN st3=> next_state<=st4;--开启OE，输出转换好的数据 WHEN st4=> next_state<=st0; WHEN OTHERS=>next_state<=st0; END CASE; END PROCESS COM1;
COM2: PROCESS(cs) BEGIN --产生输出命令 CASE cs IS
WHEN st0=> ALE<='0';START<='0';LOCK<='0';OE<='0'; WHEN st1=> ALE<='1';START<='1';LOCK<='0';OE<='0'; WHEN st2=> ALE<='0';START<='0';LOCK<='0'; OE<='0'; WHEN st3=> ALE<='0';START<='0';LOCK<='0';OE<='1'; WHEN st4=> ALE<='0';START<='0';LOCK<='1';OE<='1'; WHEN OTHERS=> ALE<='0';START<='0';LOCK<='0'; END CASE; END PROCESS COM2; REG:PROCESS(CLK,RST) BEGIN
IF(RST='1') THEN cs<=next_state;
ELSIF(CLK'EVENT AND CLK='1') THEN cs<=next_state; END IF;
END PROCESS REG; --由信号cs将当前状态值带出此进程：REG
LATCH1: PROCESS(LOCK) --此进程中，在LOCK的上升沿，将转换好的数据锁入 BEGIN
IF LOCK='1' AND LOCK'EVENT THEN REGL<=D; END IF; END PROCESS LATCH1; Q<=REGL; END behav;
10-6 用Mealy机类型，写出控制ADC0809采样的状态机。
--10-6 用Mealy机类型，写出控制ADC0809采样的状态机。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADC0809 IS
PORT(D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --来自0809转换好的8位数据 CLK: IN STD_LOGIC; --状态机工作时钟 RST: IN STD_LOGIC; --系统复位控制
EOC: IN STD_LOGIC; --转换状态指示，低电平表示正在转换 ALE:OUT STD_LOGIC; --8个模拟信号通道地址锁存信号 START:OUT STD_LOGIC; --转换开始信号
OE:OUT STD_LOGIC; --数据输出三态控制信号 ADDA:OUT STD_LOGIC; --信号通道最低位控制信号 LOCK_T:OUT STD_LOGIC; --观察数据锁存时钟
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8位数据输出 END ADC0809;
ARCHITECTURE behav OF ADC0809 IS
TYPE states IS(s0,s1,S2,s3,s4); --定义各状态子类型 SIGNAL cs,next_state: states:=s0;
SIGNAL REGL: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK: STD_LOGIC;--转换后数据输出锁存时钟信号 BEGIN
ADDA<='1';--当ADDA<='0'，选择模拟信号通道IN0；当ADDA<='1'，则选择通道IN1 LOCK_T<=LOCK;
COM: PROCESS(cs,EOC) BEGIN --规定各状态转换方式 CASE cs IS
WHEN s0=> ALE<='0';START<='0';LOCK<='0';OE<='0'; next_state<=s1; --0809初始化 WHEN s1=> ALE<='1';START<='1';LOCK<='0';OE<='0'; next_state<=s2 ;--启动采样 WHEN s2=> ALE<='0';START<='0';LOCK<='0';
IF(EOC='1') THEN next_state<=s3;OE<='1';--EOC=1转换结束，OE=1(Mealy型) ELSE next_state<=s2;OE<='0'; END IF; --未结束等待，OE=0(Mealy型) WHEN s3=> ALE<='0';START<='0';LOCK<='0';OE<='1'; next_state<=s4;--开启OE，输出转换好的数据
WHEN s4=> ALE<='0';START<='0';LOCK<='1';OE<='1';next_state<=s0; WHEN OTHERS=>next_state<=s0; END CASE; END PROCESS COM; REG:PROCESS(CLK,RST) BEGIN
IF(RST='1') THEN cs<=next_state;
ELSIF(CLK'EVENT AND CLK='1') THEN cs<=next_state; END IF;
END PROCESS REG; --由信号cs将当前状态值带出此进程：REG
LATCH1: PROCESS(LOCK) --此进程中，在LOCK的上升沿，将转换好的数据锁入 BEGIN
IF LOCK='1' AND LOCK'EVENT THEN REGL<=D; END IF; END PROCESS LATCH1; Q<=REGL; END behav;
10-7 以例10-6作为考察示例，按照表10-3，分别对此例设置不同的编码形式和安全状态机设置。给出不同约束条件下的资源利用情况(如LC、REG等)，详细讨论比较不同情况下的状态机资源利用、可靠性等方面的问题。
--(1)以例10-6为例参照表10-3的顺序编码单进程MEALY状态机。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MEALY2 IS
PORT(CLK,DIN1,DIN2,RST: IN STD_LOGIC;--时钟/串行数据/复位 Q: OUT STD_LOGIC_VECTOR(4 DOWNTO 0));--检测结果输出 END MEALY2;
ARCHITECTURE behav OF MEALY2 IS
TYPE states IS (st0,st1,st2,st3,st4);--定义各状态 attribute syn_encoding : string;
attribute syn_encoding of states : type is \ SIGNAL PST : states;
BEGIN PROCESS(CLK,RST,PST,DIN1,DIN2)
BEGIN --决定转换状态的进程 IF RST='1' THEN PST <= ST0;--复位 ELSIF CLK'EVENT AND CLK='1' THEN CASE PST IS --DIN1影响状态切换
WHEN st0=> IF DIN1='1' THEN PST<=st1; ELSE PST<=st0; END IF; IF DIN2='1' THEN Q<=\ WHEN st1=> IF DIN1='1' THEN PST<=st2; ELSE PST<=st1; END IF; IF DIN2='0' THEN Q<=\ WHEN st2=> IF DIN1='1' THEN PST<=st3; ELSE PST<=st2; END IF; IF DIN2='1' THEN Q<=\ WHEN st3=> IF DIN1='1' THEN PST<=st4; ELSE PST<=st3; END IF; IF DIN2='0' THEN Q<=\ WHEN st4=> IF DIN1='0' THEN PST<=st0; ELSE PST<=st4; END IF; IF DIN2='1' THEN Q<=\ WHEN OTHERS=> PST<=st0;Q<=\ END CASE; END IF;
END PROCESS REGCOM; END behav;
--(2)以例10-6为例参照表10-3的一位热码编码单进程MEALY状态机。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MEALY2 IS
PORT(CLK,DIN1,DIN2,RST: IN STD_LOGIC;--时钟/串行数据/复位 Q: OUT STD_LOGIC_VECTOR(4 DOWNTO 0));--检测结果输出 END MEALY2;
ARCHITECTURE behav OF MEALY2 IS
TYPE states IS (st0,st1,st2,st3,st4);--定义各状态 attribute syn_encoding : string;
attribute syn_encoding of states : type is \
SIGNAL PST : states;
BEGIN PROCESS(CLK,RST,PST,DIN1,DIN2) BEGIN --决定转换状态的进程 IF RST='1' THEN PST <= ST0;--复位 ELSIF CLK'EVENT AND CLK='1' THEN CASE PST IS --DIN1影响状态切换
WHEN st0=> IF DIN1='1' THEN PST<=st1; ELSE PST<=st0; END IF; IF DIN2='1' THEN Q<=\ WHEN st1=> IF DIN1='1' THEN PST<=st2; ELSE PST<=st1; END IF; IF DIN2='0' THEN Q<=\ WHEN st2=> IF DIN1='1' THEN PST<=st3; ELSE PST<=st2; END IF; IF DIN2='1' THEN Q<=\