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C1='1')OR(A(i-1)='1' AND B(i-1)='1' AND C1='1') THEN C1:='1'; ELSE C1:='0'; END IF; END LOOP;
SUM<=S1;COUT<=C1;
AA<=TO_STDLOGICVECTOR(TO_BITVECTOR(\ BB<=TO_STDLOGICVECTOR(TO_BITVECTOR(\ END PROCESS;
END ARCHITECTURE ONE; 3-17 举例说明GENERIC说明语句（在实体定义语句中定义类属常数）和GENERIC映射语句（在例化语句中将类属常数赋予新值）有何用处。P82
3-18 表达式C<=A+B中，A、B和C的数据类型都是STD_LOGIC_VECTOR，是否能直接进行加法运算?说明原因和解决方法。能（第一种将A、B转换成整型数相加结果再转换成逻辑位矢后送C P89；第二种使用USE IEEE.SDT_LOGIC_UNSIGNED.ALL语句打开重载运算符程序包。 P70，P130）
3-19 VHDL中有哪三种数据对象?详细说明它们的功能特点以及使用方法，举例说明数据对象与数据类型的关系。信号，变量，常量 P71
3-20 能把任意一种进制的值向一整数类型的数据对象赋值吗?如果能，怎样做? 能（若A,B,C,D是信号整数类型，A<=16#df#;B<=8#23#;C<=2#01#;D<=10）P83 3-21 回答有关BIT和BOOLEAN数据类型的问题：P59
(1)解释BIT(‘0’；‘1’)和BOOLEAN(“TRUE”，“FALSE”)类型的区别。 (2)对于逻辑操作应使用哪种类型?BIT (3)关系操作的结果为哪种类型? BOOLEAN
(4)IF语句测试的表达式是哪种类型? BOOLEAN
3-22 用两种方法设计8位比较器，比较器的输入是两个待比较的8位数A=[A7..A0]和B=[B7..80]，输出是D、E、F。当A=B时D=1；当A>B时E=1；当A --3-22 比较器的输入是两个待比较的8位数A=[A7..A0]和B=[B7..80]，输出是EQ、GT、F。当A=B时EQ=1；当A>B时GT=1；当A --第一种设计方案是常规的比较器设计方法，即直接利用关系操作符进行编程设计。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COMP IS PORT( A,B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --两个3位输入 LT: OUT STD_LOGIC; --小于输出 GT: OUT STD_LOGIC; --大于输出 EQ: OUT STD_LOGIC); --等于输出 END ENTITY COMP; ARCHITECTURE ONE OF COMP IS BEGIN PROCESS(A,B) BEGIN IF (A END ARCHITECTURE ONE; --3-22 比较器的输入是两个待比较的8位数A=[A7..A0]和B=[B7..80]，输出是EQ、GT、F。当A=B时EQ=1；当A>B时GT=1；当A --第二种设计方案是利用减法器来完成，通过减法运算后的符号和结果来判别两个被比较值的大小。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COMP IS PORT( A,B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --两个3位输入 LT: OUT STD_LOGIC; --小于输出 GT: OUT STD_LOGIC; --大于输出 EQ: OUT STD_LOGIC); --等于输出 END ENTITY COMP; ARCHITECTURE ONE OF COMP IS SIGNAL C: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL D,E,F,G: INTEGER RANGE 255 DOWNTO 0; BEGIN C<=A-B; D<=10; E<=16#D9#; F<=8#72#; G<=2#11010010#; PROCESS(A,B) BEGIN IF (C(7)='1') THEN LT<='1';ELSE LT<='0';END IF; IF (C=0) THEN EQ<='1'; ELSE EQ<='0'; IF(C(7)='0')THEN GT<='1';ELSE GT<='0';END IF; END IF; END PROCESS; END ARCHITECTURE ONE; 3-23 根据图3-19，用两种不同描述方式设计一4选1多路选择器。在设计中需要体现此电路由三个2选l多路选择器构成。解1:层次例化；解2:单层3进程。 --解1：层次例化。底层元件mux21a.vhd程序如下： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21a IS PORT(a,b,s: IN STD_LOGIC; y: OUT STD_LOGIC); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS BEGIN PROCESS(a,b,s) BEGIN IF s='0' THEN y<=a; ELSE y<=b; END IF; END PROCESS; END ARCHITECTURE one; --解1：层次例化。顶层mux41b.vhd程序如下： LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux41b IS port(X0,X1,X2,X3: IN STD_LOGIC; S0,S1: IN STD_LOGIC; OUTY: OUT STD_LOGIC); END mux41b; ARCHITECTURE bdf_type OF mux41b IS component mux21a PORT(a,b,s: IN STD_LOGIC; y: OUT STD_LOGIC); end component; signal N0,N1: STD_LOGIC; BEGIN u1: mux21a PORT MAP(a=>X0,b=>X1,s=>S0,y=>N0); u2: mux21a PORT MAP(a=>X2,b=>X3,s=>S0,y=>N1); u3: mux21a PORT MAP(a=>N0,b=>N1,s=>S1,y=>OUTY); END; --解2：单层结构mux41a.vhd程序如下： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41a IS PORT(x1,x2,x3,x4,s0,s1: IN STD_LOGIC; y: OUT STD_LOGIC); END ENTITY mux41a; ARCHITECTURE one OF mux41a IS signal N0,N1: STD_LOGIC; BEGIN com1: PROCESS(x1,x2,s0) BEGIN IF s0='0' THEN N0<=x1; ELSE N0<=x2; END IF; END PROCESS; com2: PROCESS(x3,x4,s0) BEGIN IF s0='0' THEN N1<=x3; ELSE N1<=x4; END IF; END PROCESS; com3: PROCESS(N0,N1,s1) BEGIN IF s1='0' THEN y<=N0; ELSE y<=N1; END IF; END PROCESS; END ARCHITECTURE one; 4 习 题 4-1 归纳利用Quartus II进行VHDL文本输入设计的流程：从文件输入一直到硬件功能测试。P96~P110 答：1 建立工作库文件夹和编辑设计文件；2 创建工程；3 编译前设置；4 全程编译；5 时序仿真；6 引脚锁定；7 配置文件下载；8 打开SignalTap II编辑窗口；9 调入SignalTap II的待测信号；10 SignalTap II参数设置；11 SignalTap II参数设置文件存盘；12 带有SignalTap II测试信息的编译下载；13 启动SignalTap II进行采样与分析；14 SignalTap II的其他设置和控制方法。 4-2 参考Quartus II的Help，详细说明Assignments菜单中Settings对话框的功能。 （1）说明其中的Timing Requirements & Qptions的功能、使用方法和检测途径。 （2）说明其中的Compilation Process的功能和使用方法。 （3）说明Analysis & Synthesis Setting的功能和使用方法，以及其中的Synthesis Netlist Optimization的功能和使用方法。 (1)说明其中的Timing Requirements&Qptions的功能、他用方法和检测途经。 Specifying Timing Requirements and Options (Classic Timing Analyzer) You can specify timing requirements for Classic timing analysis that help you achieve the desired speed performance and other timing characteristics for the entire project, for specific design entities, or for individual clocks, nodes, and pins. When you specify either project-wide or individual timing requirements, the Fitter optimizes the placement of logic in the device in order to meet your timing goals. You can use the Timing wizard or the Timing Analysis Settings command to easily specify all project-wide timing requirements, or you can use the Assignment Editor to assign individual clock or I/O timing requirements to specific entities, nodes, and pins, or to all valid nodes included in a wildcard or assignment group assignment. To specify project-wide timing requirements: 1. On the Assignments menu, click Settings. 2. In the Category list, select Timing Analysis Settings. 3. To specify project-wide tSU, tH, tCO, and/or tPD timing requirements, specify values under Delay requirements. 4. To specify project-wide minimum delay requirements, specify options under Minimum delay requirements. 5. Under Clock Settings, select Default required fmax. 6. In the Default required fmax box, type the value of the required fMAX and select a time unit from the list. 7. If you want to specify options for cutting or reporting certain types of timing paths globally, enabling recovery/removal analysis, enabling clock latency, and reporting unconstrained timing paths, follow these steps: 8. Click OK. To specify clock settings: 1. On the Assignments menu, click Settings. 2. In the Category list, select Timing Analysis Settings. 3. Under Clock Settings, click Individual Clocks. 4. Click New. 5. In the New Clock Settings dialog box, type a name for the new clock settings in the Clock settings name box. 6. To assign the clock settings to a clock signal in the design, type a clock node name in the Applies to node box, or click Browse... to select a node name using the Node Finder. 7. If you want to specify timing requirements for an absolute clock, follow these steps: 8. If you have already specified timing requirements for an absolute clock, and you want to specify timing requirements for a derived clock, follow these steps: 9. In the New Clock Settings dialog box, click OK. 10. In the Individual Clocks dialog box, click OK. 11. In the Settings dialog box, click OK. To specify individual timing requirements: 1. On the Assignments menu, click Assignment Editor. 2. In the Category bar, select Timing to indicate the category of assignment you wish to make. 3. In the spreadsheet, select the To cell and perform one of the following steps: ? Type a node name and/or wildcard that identifies the destination node(s) you want to assign. ? Double-click the To cell and click Node Finder to use the Node Finder to enter a node name.