内容发布更新时间 : 2024/12/23 8:50:19星期一 下面是文章的全部内容请认真阅读。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL ; ENTITY dff IS
PORT(d,clk:IN std_logic; q, qb: OUT std_logic); END dff;
ARCHITECTURE behave OF dff IS BEGIN
PROCESS(clk) BEGIN
IF AND clk'event THEN q <= ; qb<=not d; END IF;
END PROCESS; END behave;
（二十）在下面横线上填上合适的语句，完成移位寄存器的设计。 说明：4位串入-串出移位寄存器有有1个串行数据输入端（di）、1个串行数据输出输出端（do）和1个时钟输入端（clk） LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY siso IS
PORT(di: IN std_logic; clk:IN std_logic; do:OUT std_logic); END siso;
ARCHITECTURE a OF siso IS
SIGNAL q: std_logic_vector(3 DOWNTO 0); BEGIN
PROCESS(clk,di) BEGIN
IF clk’ event AND clk=’1’ THEN q(0)<= ; for loop q(i)<= ; END IF; END PROCESS; do<=q(3); END a;
（二十一）在下面横线上填上合适的语句，完成同步22进制计数器的设计。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY counter22 IS
PORT( clk: IN std_logic; ch, c: OUT std_logic;
qb1, qa1: OUT std_logic_vector(3 DOWNTO 0)); END;
ARCHITECTURE behav OF counter22 IS
SIGNAL qb, qa: std_logic_vector(3 DOWNTO 0); SIGNAL cin: std_logic; BEGIN qb1<=qb; qa1<=qa; PROCESS(clk) BEGIN
IF clk'event AND clk='1' THEN
IF (qa= ) OR (qb=2 AND qa=1) THEN qa<=\ELSIF qa= THEN cin<='1'; qa<=qa+1; ELSE qa<= ; cin<='0'; END IF; END IF; END PROCESS;
PROCESS(cin, clk) BEGIN
IF clk'event AND clk='1' THEN
IF (qb=2 AND qa=1) THEN qb<= ; c<='1'; ELSE c<= ; END IF;
IF cin='1' THEN qb<= ; END IF; END IF;
END PROCESS; ch<=cin; END;
（二十二）在下面横线上填上合适的语句，完成一个“01111110”序列发生器的设计。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; USE ieee.std_logic_arith.ALL;
ENTITY senqgen IS
PORT(clk,clr,clock:IN std_logic; zo:OUT std_logic); END;
ARCHITECTURE art OF senqgen IS
SIGNAL count:std_logic_vector(2 DOWNTO 0); SIGNAL z:std_logic:='0'; BEGIN
PROCESS(clk,clr) BEGIN
IF clr='1' THEN count<=\ ELSE
IF clk='1' AND clk'event THEN
IF count= THEN count<=\ ELSE count<=count+1; END IF; END IF; END IF;
END PROCESS; PROCESS(count) BEGIN
CASE count IS
WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \
WHEN OTHERS=>z<= ; END CASE; END PROCESS; PROCESS(clock,z) BEGIN
IF clock='1' AND clock'event THEN zo<= ; END IF; END PROCESS; END art;
（二十三）在下面横线上填上合适的语句，完成一个“01111110”序列信号检测器的设计。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY detect IS
PORT( dataIN:IN std_logic; clk:IN std_logic; q:BUFFER std_logic); END detect;
ARCHITECTURE art OF detect IS
type statetype IS (s0,s1,s2,s3,s4,s5,s6,s7,s8); BEGIN
PROCESS(clk)
VARIABLE : ; BEGIN q<='0';
CASE present_state IS WHEN s0=>
IF dataIN='0' THEN present_state:=s1; ELSE present_state:=s0; END IF; WHEN s1=>
IF dataIN='1' THEN present_state:=s2; ELSE present_state:=s1; END IF;
WHEN s2=>
IF dataIN='1' THEN present_state:=s3; ELSE present_state:=s1; END IF;
WHEN s3=>
IF dataIN='1' THEN present_state:=s4; ELSE present_state:=s1; END IF;
WHEN s4=>
IF dataIN='1' THEN present_state:=s5; ELSE present_state:=s1; END IF;
WHEN s5=>
IF dataIN='1' THEN present_state:=s6; ELSE present_state:=s1; END IF;
WHEN s6=>
IF dataIN='1' THEN present_state:=s7; ELSE present_state:=s1; END IF;
WHEN s7=>
IF dataIN='0' THEN present_state:=s8; q<='1'; ELSE present_state:=s0; END IF; WHEN s8=>
IF dataIN='0' THEN present_state:= ; ELSE present_state:= ; END IF; END CASE;
clk='1'; END PROCESS; END art;
（二十四）在下面横线上填上合适的语句，完成序列信号发生器的设计。
说明：带异步复位为clr，时钟端为clk，输出端为q，串行输出指定序列（低位先出）。 LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY senqgen IS
PORT(clr,clk:IN std_logic; q:OUT std_logic); END senqgen;
ARCHITECTURE beha OF senqgen IS
SIGNAL q_temp:std_logic_vector(2 DOWNTO 0); BEGIN
PROCESS(clk,clr) BEGIN
IF clr='1' THEN q_temp<=\
(clk'event AND clk='1') THEN IF q_temp=\ q_temp<=q_temp+1; END IF;
; END PROCESS; PROCESS(q_temp) BEGIN
CASE q_temp IS
WHEN \WHEN \WHEN \WHEN \WHEN OTHERS=> ; END CASE; END PROCESS; END beha;
（二十五）在下面横线上填上合适的语句，完成七人表决器的设计。