内容发布更新时间 : 2024/12/23 8:40:30星期一 下面是文章的全部内容请认真阅读。
说明:一个带输出显示的七人表决器(两种结果:同意,反对)。 LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY biaojue7 IS
PORT(d:IN std_logic_vector(0 TO 6); rled,gled:OUT std_logic;
ledseg:OUT std_logic_vector( 6 DOWNTO 0) ); END;
ARCHITECTURE bev OF biaojue7 IS BEGIN PROCESS(d)
VARIABLE count:INteger RANGE 0 TO 7 ; BEGIN
count:= ; for loop
IF d(i)='1' THEN count:= ; ELSE count:=count; END IF; END loop;
IF count> THEN gled<='1'; rled<='0'; ELSE gled<='0'; rled<='1'; END IF;
CASE count IS
WHEN 0=> ledseg<=\WHEN 1=> ledseg<=\WHEN 2=> ledseg<=\WHEN 3=> ledseg<=\WHEN 4=> ledseg<=\WHEN 5=> ledseg<=\WHEN 6=> ledseg<=\WHEN 7=> ledseg<=\END CASE; END PROCESS; END bev;
(二十六)在下面横线上填上合适的语句,完成有限状态机的设计。 说明:状态转换图如右图,S0~S3为状态号,圈内为输出。 LIBRARY 1EEE;
USE IEEE.STD_ LOGIC_1164.ALL;
ENTITY s_ machine IS
port( clk,reset:IN STD_LOGIC;
inputs :IN STD_LOGIC_VECTOR (0 TO 1); outputs :OUT INTEGER range (0 to 15 ); END s_ machine;
ARCHITECTURE behav OF s_machine IS
Type states is (s0, s1, s2, s3); SIGNAl curcent_state,next_state:states; BEGIN
REG: PROCESS (reset,clk) --状态切换 BEGIN
IF reset = ‘1’ THEN current_ state <= s0; ELSIF clk=’l’AND clk‘EVENT THEN Current_ state <= next_ state; END IF; END PROCESS;
COM:PROCESS(current_ state, inputs)--下一状态、 Begin
CASE current_ state IS
WHEN s0 => outputs<= ; IF inputs=”00” THEN next_ state<=s0; ELSE next_ state<=sl; END IF;
WHEN sl=> outputs<=8;
IF inputs= THEN next_ state<= ; ELSE next_state<=s2; END If;
WHEN S2=> outputs<=12;
IF inputs=“11” THEN next_state<=s0; ELSE next_state<= s3; END IF;
when s3=> OUTPUTS<=14;
If inputs = “11” THen next_state <=s3;; ELSE next state <=s0; END IF; END case; ; END behav;
(二十七)在下面横线上填上合适的语句,完成移位寄存器74166的设计。 LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL; ENTITY ttl74166 IS
PORT( a,b,c,d,e,f,g,h:IN std_logic; --8位并行输入信号 clk:IN std_logic; --时钟信号 reset:IN std_logic; --复位信号 se:IN std_logic; --串行输入信号 fe:IN std_logic; --时钟信号禁止端 sl:IN std_logic; --移位装载控制端 q:OUT std_logic); --串行输出信号 END ttl74166;
ARCHITECTURE art OF ttl74166 IS
SIGNAL tmpreg8:std_logic_vector(7 DOWNTO 0); BEGIN
PROCESS(clk,reset,sl,fe) BEGIN
IF reset='1' THEN tmpreg8<= ; q<=tmpreg8(7); ELSIF clk'event AND clk='1' THEN IF fe='0' THEN IF sl='0' THEN tmpreg8(0)<=a; tmpreg8(1)<=b; tmpreg8(2)<=c; tmpreg8(3)<=d; tmpreg8(4)<=e; tmpreg8(5)<=f; tmpreg8(6)<=g; tmpreg8(7)<=h;
sl='1' THEN
for i IN tmpreg8'high DOWNTO loop tmpreg8(i)<= ; END loop;
tmpreg8(tmpreg8'low)<= ; q<= ; END IF; END IF; END IF;
END PROCESS; END art;
(二十八)在下面横线上填上合适的语句,完成8位双向总线缓冲器的设计。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY tri_bigate IS
PORT( a,b: INOUT std_logic_vector(7 DOWNTO 0); en, dr: IN std_logic); END;
ARCHITECTURE rtl OF tri_bigate IS
SIGNAL aOUT, bOUT:std_logic_vector(7 DOWNTO 0); BEGIN
PROCESS(a, dr, en)
BEGIN IF (en=‘0’) AND (dr=‘1’) THEN bOUT<=a; ELSE
bOUT<=“ZZZZZZZZ”; END IF; b<=bOUT; END PROCESS;
PROCESS(b, dr, en) BEGIN
IF (en=‘0’) AND (dr=‘0’) THEN aOUT<= ; ELSE
aOUT<= ; END IF;
a<= ; END PROCESS; END;
(二十九)在下面横线上填上合适的语句,完成4位串入/并出移位寄存器的设计。 说明:4位串入/并出移位寄存器可以用d触发器组成。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL ; ENTITY dff IS
PORT(d,clk:IN std_logic; q: OUT std_logic); END dff;
ARCHITECTURE behave OF dff IS BEGIN PROCESS(clk) BEGIN
IF clk= '0' AND clk'event THEN q <=d; END IF; END PROCESS; END behave;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY shift IS
PORT(a,clk: IN std_logic; d : OUT std_logic); END shift;
ARCHITECTURE shift1 OF shift IS COMPONENT dff1
PORT (d,clk: IN std_logic; q: OUT std_logic); END COMPONENT ;
SIGNAL z:std_logic_vector(0 TO 4); BEGIN
z(0)<= ;
g1:for GENERATE
dffx:dff1 PORT MAP (z(i),clk, ); END GENERATE; d<= ; END shift1;
(三十)在下面横线上填上合适的语句,完成4位异步计数器的设计。 说明:4位异步计数器可以用d触发器器组成。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL ; ENTITY dff1 IS
PORT(d,clk:IN std_logic; q, qb: OUT std_logic); END dff1;
ARCHITECTURE behave OF dff1 IS BEGIN PROCESS(clk) BEGIN
IF clk= '1' AND clk'event THEN q <=d; qb<=not d; END IF; END PROCESS; END behave; LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY rplcont IS
PORT( clk : IN std_logic;
count : OUT std_logic_vector(3 DOWNTO 0)); END rplcont;
ARCHITECTURE rplcont OF rplcont IS