内容发布更新时间 : 2026/3/23 20:09:07星期一 下面是文章的全部内容请认真阅读。
COMPONENT dff1
PORT (clk,d:IN std_logic; q,qb:OUT std_logic); END COMPONENT ;
SIGNAL count_IN_bar:std_logic_vector(4 DOWNTO 0); BEGIN
count_IN_bar(0)<=clk;
gen1:for i IN 0 TO 3 GENERATE
u:dff1 PORT MAP (clk=> , d=> , q=> ,qb=> ); END GENERATE; END rplcont;
（三十一）在下面横线上填上合适的语句，完成交通灯控制器的设计。
说明：红、黄、绿灯分别亮10秒，状态0时东西绿灯亮，南北红灯亮；状态1时东西绿、黄灯亮，南北红灯亮；状态2时东西红灯亮，南北绿灯亮；状态3时东西红灯亮，南北绿、黄灯亮。
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY trafficled1 IS
PORT (clk, reset: IN std_logic;
q: OUT std_logic_vector(11 DOWNTO 0) ); END;
ARCHITECTURE one OF trafficled1 IS
SIGNAL y_ewsn, g_ewsn, r_ewsn:std_logic_vector(3 DOWNTO 0); SIGNAL count:integer RANGE 0 TO 9; SIGNAL state:integer RANGE 0 TO 3; BEGIN
PROCESS(reset, clk,count) BEGIN
IF reset='1' THEN count<=0; state<=0;
ELSIF clk'event AND clk='1' THEN count<=count+1;
IF (count= ) THEN state <=state+1; END IF;
IF state> THEN state <=0; END IF; END IF;
CASE state IS
WHEN 0 => y_ewsn<=\WHEN 1 => y_ewsn<=\WHEN 2 => y_ewsn<=\WHEN 3=> y_ewsn<=\WHEN OTHERS=> ;
END CASE; END PROCESS;
q(0)<=r_ewsn(0); q(1)<=g_ewsn(0); q(2)<=y_ewsn(0) ; q(3)<=r_ewsn(2); q(4)<=g_ewsn(2); q(5)<=y_ewsn(2) ; q(6)<=r_ewsn(1); q(7)<=g_ewsn(1); q(8)<=y_ewsn(1) ; q(9)<=r_ewsn(3); q(10)<=g_ewsn(3); q(11)<=y_ewsn(3) ; END;
（三十二）在下面横线上填上合适的语句，完成8位数字比较器的设计。
ENTITY COMP IS PORT
(a,b: IN RANGE 0 T0 ; aequalb, agreatb, alessb : OUT BIT); END COMP;
ARCHITECTURE behave OF COMP IS BEGIN
aequalb＜＝‘1’ WHEN a＝b ELSE‘0’; agreatb＜＝‘1’ WHEN a＞b ELSE‘0’; alessb＜＝‘1’ WHEN a＜b ELSE‘0’; END behave;
（三十三）在下面横线上填上合适的语句，完成一个16个字节的堆栈的设计。 说明：堆栈有复位信号、压栈/弹栈信号、堆栈满信号、数据输入/输出口。 LIBRARY ieee； USE ieee.std_logic_1164.ALL； USE ieee.std_logic_signed.ALL；
ENTITY stack IS PORT
( datain : IN std_logic_vector (7 DOWNTO 0 );
push , pop , reset , clk : IN std_logic; stackfull : OUT std_logic;
dataout : BUFFER std_logic_vector (7 DOWNTO 0 )); END stack;
ARCHITECTURE a OF stack IS
TYPE arraylogic IS ARRAY (15 DOWTO 0) OF std_logic_vector (7 DOWNTO 0 ); --定义一个16字节数据类型
SIGNAL data : arraylogic； -- 此处定义了data为一个数组16×8 SIGNAL stackflag : std_logic_vector (15 DOWNTO 0 ); --定义堆栈标志，每一字节有数据为1，无数据为0 BEGIN
stackfull＜＝ ; --字节0为栈底
PROCESS (clk , nreset , pop , push) BEGIN
IF reset = ‘1’ THEN
stackflag＜＝( OTHERS => ‘0’ ); dataout＜＝( OTHERS => ‘0’ ); FOR i IN 0 TO 15 LOOP
data ( i ) ＜＝ ; END LOOP;
ELSIF clk’event AND clk = ‘1’ THEN
IF push = ‘1’ AND pop= ‘0’ THEN -- push FOR i IN 0 TO 14 LOOP
data ( i ) ＜＝ ; END LOOP;
data (15) ＜＝ ;
stackflag＜＝‘1’ & stackflag(15 DOWNTO 1 );
ELSIF push = ‘0’ AND pop= ‘1’ THEN -- pop dataout＜＝data (15);
FOR i IN 15 DOWNTO 1 LOOP data ( i ) ＜＝ ; END LOOP；
stackflag＜＝stackflag ( DOWNTO 0 ) & ‘0’; END IF；
END IF； END PROCESS; END a;
（三十四）在下面横线上填上合适的语句，完成一个8位分频器的设计。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PULSE IS
PORT ( CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR (7 DOWNTO 0); FOUT : OUT STD_LOGIC ); END;
ARCHITECTURE one OF PULSE IS SIGNAL FULL : STD_LOGIC; BEGIN
P_REG: PROCESS(CLK)
CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
IF CLK’EVENT AND CLK = ‘1’ THEN IF CNT8 = \ CNT8 := ; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8 FULL <= '1'; --同时使溢出标志信号FULL输出为高电平 ELSE CNT8 := ; --否则继续作加1计数
FULL <= '0'; --且输出溢出标志信号FULL为低电平 END IF; END IF;
END PROCESS P_REG;
P_DIV: PROCESS( ) VARIABLE CNT2 : STD_LOGIC; BEGIN
IF FULL'EVENT AND FULL = '1' THEN
CNT2 <= ; --如果溢出标志信号FULL为高电平，D触发器输出取反 IF CNT2 = '1' THEN FOUT <= '1'; ELSE FOUT <= '0'; END IF; END IF;
END PROCESS P_DIV; END;
（三十五）在下面横线上填上合适的语句，完成一个10线－4线优先编码器的设计。
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY coder IS
PORT ( din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END coder;
ARCHITECTURE behav OF CODER IS
SIGNAL SIN : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
PROCESS ( ) BEGIN
IF (din(9)='0') THEN SIN <= \
(din(8)=’0’) THEN SIN <= \ ELSIF (din(7)='0') THEN SIN <= \ ELSIF (din(6)='0') THEN SIN <= \ ELSIF (din(5)='0') THEN SIN <= \ ELSIF (din(4)='0') THEN SIN <= \ ELSIF (din(3)='0') THEN SIN <= \ ELSIF (din(2)='0') THEN SIN <= \ ELSIF (din(1)='0') THEN SIN <= \ ELSE SIN <= ;
； END PROCESS ； Output <= sin ； END behav;
三十六）在下面横线上填上合适的语句，完成一个摩尔状态机的设计。 说明:状态机的状态图见图a,状态结构图见图b.
Library ieee;
Use ieee.std_logic_1164.all; Entity mooreb is
Port (clk, reset : in std_logic;
Ina : in std_logic_vector (1 downto 0); Outa : out std_logic_vector (3 downto 0) ); End mooreb;
Architecture one of mooreb is
Type ms_state is (st0, st1, st2, st3); Signal c_st, n_st : ; Begin
Process (clk, reset) Begin
If reset = ‘1’ then c_st <= st0;
Elsif clk’event and clk = ‘1’ then c_st <= ; End if; End process; Process (c_st) Begin
Case c_st is
When st0 => if ina = “00” then n_st <= st0; Else n_st <= st1; End if;
Outa <= “0101”;
When st1 => if ina = “00” then n_st <= st1; Else n_st <= st2; End if;
Outa <= “1000”;
When st2 => if ina = “11” then n_st <= ; Else n_st <= st3; End if;
Outa <= “1100”;
When st3 => if ina = “11” then n_st <= ; Else n_st <= st0; End if;
Outa <= ;