VHDL复习题

内容发布更新时间 : 2024/12/24 8:02:00星期一 下面是文章的全部内容请认真阅读。

. USE IEEE. .ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT ( CLK : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) ; END CNT10;

ARCHITECTURE bhv OF IS SIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS (CLK) IF THEN -- 边沿检测 IF Q1 > 10 THEN Q1 <= (OTHERS => '0'); -- 置零 ELSE Q1 <= Q1 + 1 ; -- 加1 END IF; END IF; END PROCESS ; ; -- 输出 END bhv;

2.以下程序是BCD码表示0~99计数器的VHDL描述,试补充完整。 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE ; ENTITY cnt100b is port( clk, rst, en : in std_logic; cq : out std_logic_vector(7 downto 0); -- 计数输出 cout: out std_logic); -- 进位输出 END ENTITY cnt100b;

bhv of cnt100b is BEGIN PROCESS (clk, rst, en) cqi : std_logic_vector(7 downto 0); BEGIN if rst = '1' then cqi := ; -- 计数器清零 else if then -- 上升沿判断 if en = '1' then if cqi(3 downto 0) < \ -- 比较低4位 ; -- 计数加1

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.

else if cqi(7 downto 4) < \-- 比较高4位 cqi := cqi + 16; else cqi := (others => '0'); end if;

-- 低4位清零

cqi ( ) := “0000”;

end if; end if; ; end if; if cqi = “ ” then cout <= '1'; else cout <= '0'; end if; ; END PROCESS;

-- 判断进位输出

END ARCHITECTURE bhv;

3.以下程序是多路选择器的VHDL描述,试补充完整。 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY bmux IS

PORT ( sel : STD_LOGIC;

A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Y

: STD_LOGIC_VECTOR(7 DOWNTO 0)) ;

END bmux;

ARCHITECTURE bhv OF bmux IS BEGIN

y <= A when sel = '1' ; END ;

4.以下程序是10/4线优先编码器的VHDL描述,试补充完整。 LIBRARY IEEE ;

USE IEEE. .ALL;

ENTITY coder IS

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. PORT ( din : IN STD_LOGIC_VECTOR( ); output : STD_LOGIC_VECTOR(3 DOWNTO 0) ); END coder;

ARCHITECTURE behav OF IS

SIGNAL SIN : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

PROCESS ( ) BEGIN

IF (din(9)='0') THEN SIN <= \ ELSIF ( ) THEN SIN <= \ ELSIF (din(7)='0') THEN SIN <= \ ELSIF (din(6)='0') THEN SIN <= \ ELSIF (din(5)='0') THEN SIN <= \ ELSIF (din(4)='0') THEN SIN <= \ ELSIF (din(3)='0') THEN SIN <= \ ELSIF (din(2)='0') THEN SIN <= \ ELSIF (din(1)='0') THEN SIN <= \ ELSE ; ; END PROCESS ; ; END behav; 五、程序分析题

1.以下程序是四选一数据选择器的VHDL描述,请分析程序并画出原理图或详述其功能

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY multi_4v IS

PORT(S : IN STD_LOGIC_VECTOR (1 DOWNTO 0); A,B,C,D : IN STD_LOGIC; Y : OUT STD_LOGIC); END multi_4v;

ARCHITECTURE a OF multi_4v IS BEGIN

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. PROCESS BEGIN

IF (S=\ Y <= A;

ELSIF (S=\ Y <= B;

ELSIF (S=\ Y <= C;

ELSIF (S=\ Y <= D; END IF; END PROCESS; END a;

2.下面是同步清零可逆计数器的程序,请分析程序并画出原理图或详述其功能 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY countud IS

PORT(clk :IN STD_LOGIC; clr :IN STD_LOGIC; dire :IN STD_LOGIC;

q :BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0)); END countud;

ARCHITECTURE a OF countud IS BEGIN

PROCESS(clk) BEGIN

IF clk'event AND clk='1' THEN IF clr='0' THEN

q<=\ ELSIF dire='1' THEN

q<=q+1;

ELSE q<=q-1; END IF;

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. END IF; END PROCESS; END a;

3.以下程序是上升沿计数器的VHDL描述,请分析程序并画出原理图或详述其功能

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY three IS

PORT(clk,d : IN

STD_LOGIC;

Dout : OUT STD_LOGIC );

END;

ARCHITECTURE bhv OF three IS

SIGNAL tmp: STD_LOGIC; BEGIN

P1: PROCESS(clk) BEGIN

IF rising_edge(clk) THEN

Tmp <= d; dout <= tmp;

END IF;

END PROCESS P1; END bhv; 六、程序阅读理解题

1.以下程序能实现加和减功能的计数器,请在划线空白处注释该句的功能 Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all;

Entity up_down is Port(clk,rst,en,up: in std_logic;

Sum: Cout:

out std_logic);

out std_logic_vector(2 downto 0);

End up_down;

Architecture a of up_down is Signal count: std_logic_vector(2 downto 0); Begin

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