ALTERA SERDES IP瀹炰緥搴旂敤 - 鐧惧害鏂囧簱

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涓婁紶

棣栭〉

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ALTERA SERDES IP

瀹炰緥搴旂敤

 

 

涓轰簡鐔熸倝

ALTERA

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SERDES IP

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璇曠潃鐢熸垚

ALT_LVDS_RX

鍜?/p>

ALT_LVDS_TX

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IP

鍋氫釜鍥炵幆浠?/p>

鐪熸祴璇曘�?/p>

骞冲彴锛?/p>

QUARTUS 10.1 +Moelsim6.6SE 

 

FPGA:Stratix IV 820 

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Stratix 

IV 820

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涓�

 

LVDS

鐢靛钩

 

 

LVDS

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浣庡姛鑰楅�氱敤鐨?/p>

I/O

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Stratix IV FPGA

瑕佹眰

2.5V Vccio

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LVDS

瑕佹眰杈撳叆

buffer

鐨?/p>

2

鏍逛俊鍙蜂箣闂存湁

100

惟

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Stratix IV FPGA

浣?/p>

鐢?/p>

OCT(on-chip 

differential 

termination)

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100

惟

宸�鍒嗙粓绔�鐢甸樆銆備絾

鏄�杩欎簺鐗囦笂鍙�閫夌殑

100

惟

宸�鍒嗙粓绔�鐢甸樆鍙�瀛樺湪浜�

Stratix 

IV 

FPGA

鐨?/p>

row 

banks

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6-31

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