EDA VHDL 4位全加器实验报告解析 下载本文

内容发布更新时间 : 2024/4/24 21:38:53星期一 下面是文章的全部内容请认真阅读。

PORT ( CLKK : IN STD_LOGIC; CNT_EN : OUT STD_LOGIC; RST_CNT : OUT STD_LOGIC; Load : OUT STD_LOGIC ); END FTCTRL;

ARCHITECTURE behav OF FTCTRL IS SIGNAL Div2CLK : STD_LOGIC ; BEGIN PROCESS (CLKK) BEGIN IF CLKK'EVENT AND CLKK = '1' THEN Div2CLK <= NOT Div2CLK; END IF; END PROCESS; PROCESS (CLKK,Div2CLK) BEGIN IF CLKK = '0' AND Div2CLK ='0' THEN RST_CNT <= '1'; ELSE RST_CNT <= '0'; END IF; END PROCESS; Load <= NOT Div2CLK; CNT_EN <= Div2CLK; END behav;

计数器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER32B IS PORT( FIN : IN STD_LOGIC; CLR : IN STD_LOGIC; ENABL : IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );

END COUNTER32B;

ARCHITECTURE behav OF COUNTER32B IS SIGNAL CQI : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN PROCESS(FIN ,CLR ,ENABL) BEGIN IF CLR = '1' THEN CQI <= (OTHERS => '0');

ELSIF FIN'EVENT AND FIN = '1' THEN IF ENABL = '1' THEN CQI <= CQI + 1; END IF; END IF; END PROCESS; DOUT <= CQI; END behav;

锁存器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG32B IS PORT( LK : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END REG32B;

ARCHITECTURE behav OF REG32B IS BEGIN PROCESS(LK,DIN) BEGIN IF LK'EVENT AND LK='1' THEN DOUT <= DIN; END IF; END PROCESS; END behav;

频率计顶层文件

LIBRARY IEEE; LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY FREQTEST IS --频率计顶层文件 PORT ( CLK1HZ : IN STD_LOGIC; --输入引脚,输入1HZ信号作为时钟信号 FSIN : IN STD_LOGIC; --待测频率信号 DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --计数结果输出 );

END FREQTEST ;

ARCHITECTURE struc OF FREQTEST IS COMPONENT FTCTRL --测频控制电路 PORT( CLKK :IN STD_LOGIC; --1HZ输入信号 CNT_EN : OUT STD_LOGIC; --0.5HZ信号,产生1s的计数时间 RST_CNT : OUT STD_LOGIC; --计数器清零信号,1HZ与使能信号同为低时

清零 Load : OUT STD_LOGIC --0.5HZ锁存信号 );

END COMPONENT;

COMPONENT COUNTER32B --32位计数器 PORT( FIN :IN STD_LOGIC; --计数信号,与FSIN相连,输入待测信号 CLR : IN STD_LOGIC; --清零信号,与RST_CNT相连 ENABL : IN STD_LOGIC; --计数使能信号,与CNT_EN相连 DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --计数结果输出,输入到锁存器中 );

END COMPONENT; COMPONENT REG32B --32位锁存器 PORT( LK :IN STD_LOGIC; --锁存器使能输入0.5HZ信号,与Load相连 DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --计数结果输入 DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --计数结果输出 );

END COMPONENT; SIGNAL TSTEN1 : STD_LOGIC; SIGNAL CLR_CNT1 : STD_LOGIC; SIGNAL Load1 : STD_LOGIC; SIGNAL DTO1 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL CARRY_OUT1 : STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN

U1: FTCTRL PORT MAP( CLKK => CLK1HZ,CNT_EN => TSTEN1, RST_CNT => CLR_CNT1,Load => Load1 ); U2: REG32B PORT MAP( LK => Load1,DIN => DTO1,DOUT =>DOUT );

U3: COUNTER32B PORT MAP( FIN =>FSIN,CLR => CLR_CNT1, ENABL => TSTEN1,DOUT =>DTO1 ); END struc;