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实验名称: 译码器的VHDL设计
二、用WHEN_ELSE语句编写具有使能端的3-8译码器 1.实体框图
2.程序设计
①编译前的程序
Entity Dec38A is port(s1,s2,s3:in bit; A2,A1,A0:in bit;
Y:out bit_vector(7 downto 0)); End Dec38A;
Architecture two of Dec38A is
Begin
Y<=\ when s1s2s3=\else
\ when s1s2s3=\else
\ when s1s2s3=\else
\ when s1s2s3=\else
\ when s1s2s3=\else
\ when s1s2s3=\else
\ when s1s2s3=\else
\ when s1s2s3=\else
\ ; End architecture two;
and A2A1A0=\and A2A1A0=\and A2A1A0=\and A2A1A0=\and A2A1A0=\and A2A1A0=\and A2A1A0=\and A2A1A0=\ ②程序编译错误情况 错误1:
Error (10482): VHDL error at Dec38A.vhd(15): object \is used but not declared
错误2:
Error (10482): VHDL error at Dec38A.vhd(15): object \is used but not declared
③正确的程序
Entity Dec38A is port(s1,s2,s3:in bit; A2,A1,A0:in bit;
Y:out bit_vector(7 downto 0)); End Dec38A;
Architecture two of Dec38A is signal s:bit_vector(1 to 3);
signal A:bit_vector(2 downto 0); Begin
s<=s1 & s2 & s3; A<=A2 & A1 & A0;
Y<=\ when s=\ and A=\ else \ when s=\ and A=\ else \ when s=\ and A=\ else \ when s=\ and A=\ else \ when s=\ and A=\ else \ when s=\ and A=\ else \ when s=\ and A=\ else \ when s=\ and A=\ else \ ; End architecture two;
3.仿真波形图
4.仿真波形分析
S1、S2、S3是使能端,A0、A1、A2是选通端,Y7~Y0是输出端 当S1、S2、S3为100时,译码器工作 A=\时, Y=\
A=\时,Y= \A=\时,Y=\A=\时,Y=\A=\时,Y=\A=\时,Y= \A=\时,Y=\
A=\时,Y= \;使能端无效时为
\ ;
二、用WHEN_ELSE语句实现驱动共阳极数码管七段显示译码器 1.实体框图
2.程序设计
①编译前的程序
Library ieee;
Use ieee.std_logic_1164.all; Entity DD is
port(A: in std_logic_vector(3 downto 0);
DOUT:out std_logic_vector(6 downto 0));
End DD;
Architecture three of DD is Begin
DOUT<=\ when A=\ else \ when A=\ else \ when A=\ else \ when A=\ else \ when A=\ else \ when A=\ else \ when A=\ else \ when A=\ else \ when A=\ else \ when A=\ else \ ; End architecture three;
②程序编译错误情况 错误:无
3.仿真波形图
4.仿真波形分析
A为输入端,DOUT为输出端
A=\时,DOUT=\,显示0
A=\时,DOUT= \,显示1 A=\时,DOUT= \,显示2 A=\时,DOUT= \,显示3 A=\时,DOUT=\,显示4
A=\时,DOUT= \,显示5 A=\时,DOUT= \,显示6 A=\时,DOUT= \,显示7 A=\时,DOUT= \,显示8 A=\时,DOUT= \,显示9 否则不满足要求时,输出 \,不显示 ;