内容发布更新时间 : 2024/11/19 10:18:54星期一 下面是文章的全部内容请认真阅读。
END PROCESS; END BEHAV；
9、完成8位奇偶校验器的设计。 LIBRARY IEEE；
USE IEEE.STD_LOGIC_1164.ALL； ENTITY P_CHECK IS
PORT (A：IN STD_LOGIC_VECTOR(7 DOWNTO 0)； Y：OUT STD_LOGIC)； END P_CHECK；
ARCHITECTURE ART OF P_CHECK IS BEGIN
PROCESS(A)
variable TMP:STD_LOGIC; BEGIN
TMP :='0'; --TMP <='0';
FOR N IN 0 TO 7 LOOP --TMP <=TMP XOR A(N); TMP :=TMP XOR A(N); END LOOP; Y<= TMP;
END PROCESS; END ART;
10、写出具有同步清零功能、时钟上升沿触发的D触发器的VHDL描述。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL； ENTITY DFF IS
PORT(D, CLK，RESET:IN STD_LOGIC; Q:OUT STD_LOGIC); END DFF;
ARCHITECTURE BEHAV OF DFF IS BEGIN
PROCESS(D,CLK,RESET) BEGIN
IF RESET=?1? THEN Q<=?0?;
ELSIF CLK?EVENT AND CLK=?1?THEN Q<=?D?; END IF; END PROCESS; END BEHAV；
11、设计4-2线优先编码器设计(输入高电平有效，输出高电平有效）。 library ieee;
use ieee.std_logic_1164.all; entity encoder_4 is
port( in0,in1,in2,in3: in std_logic; out0,out1: out std_logic );
end;
architecture bh of encoder_4 is
signal ou: std_logic_vector(1 downto 0); begin
ou<=\ \ \ \
out1<=ou(1); out0<=ou(0); end; 12、设计以4位2进制全加器。 library ieee;
use ieee.std_logic_1164.all; entity adder_4 is
port(a,b: in std_logic_vector(3 downto 0); cin: in std_logic;
c: out std_logic_vector(3 downto 0); carry_out: out std_logic); end;
architecture bh of adder_4 is begin
process(a,b,cin)
variable ca: std_logic;
variable sum_tmp: std_logic_vector(3 downto 0); begin
ca:=cin;
for i in 0 to 3 loop
sum_tmp(i):=a(i) xor b(i) xor ca;
ca:=(a(i) and b(i)) or (a(i) and ca) or (ca and b(i)); end loop;
c<=sum_tmp; carry_out<=ca; end process; end;
13、完成JK触发器的设计。 library ieee;
use ieee.std_logic_1164.all; entity jkff is
port(j,k,ck: in std_logic; q,nq: out std_logic); end;
architecture bh of jkff is signal q_tmp: std_logic; begin
process(ck) begin
if ck'event and ck='1' then
if (j='1' and k='0') then q_tmp<='1'; elsif(j='0' and k='1') then q_tmp<='0';
elsif(j='1' and k='1') then q_tmp<=not q_tmp; end if; end if; end process;
q<=q_tmp; nq<=not q_tmp; end;
14、完成带异步清零端子的JK触发器的设计。 library ieee;
use ieee.std_logic_1164.all; entity jkff is
port(j,k,ck,cl: in std_logic; q,nq: out std_logic); end;
architecture bh of jkff is signal q_tmp: std_logic; begin
process(cl,ck) begin
if cl='1' then q_tmp<='0'; elsif ck'event and ck='1' then
if (j='1' and k='0') then q_tmp<='1'; elsif(j='0' and k='1') then q_tmp<='0';
elsif(j='1' and k='1') then q_tmp<=not q_tmp; end if; end if; end process;
q<=q_tmp; nq<=not q_tmp; end;
15、完成60进制计数器的设计。 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt_60 is
port(clk,rst:in std_logic;
qout: out std_logic_vector(7 downto 0)); end;
architecture bh of cnt_60 is
signal qh,ql:std_logic_vector(3 downto 0); begin
process(clk,rst) begin
if (rst='1') then ql<=\ elsif (clk'event and clk='1') then if (ql=9) then ql<=\ if (qh=5) then qh<=\ else qh<=qh+1; end if;
else ql<=ql+1; end if; end if;
qout<=qh & ql; end process; end;
16、完成带同步清零端子的T触发器的设计。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL； ENTITY DFF IS
PORT(t, CLK，RESET:IN STD_LOGIC; Q:INOUT STD_LOGIC); END DFF;
ARCHITECTURE BEHAV OF DFF IS BEGIN
PROCESS(t,CLK,RESET) BEGIN
IF CLK?EVENT AND CLK=?1?THEN ELSIF RESET=?1? THEN Q<=?0?; ELSIf t=?1? then Q<=NOT Q; END IF; END IF; END PROCESS; END BEHAV；
17、完成带异步清零端子的T触发器的设计。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL； ENTITY DFF IS
PORT(t, CLK，RESET:IN STD_LOGIC; Q:INOUT STD_LOGIC); END DFF;
ARCHITECTURE BEHAV OF DFF IS BEGIN
PROCESS(t,CLK,RESET) BEGIN
IF RESET=?1? THEN Q<=?0?; ELSIF CLK?EVENT AND CLK=?1?THEN If t=?1? then Q<=NOT Q;
END IF; END IF; END PROCESS; END BEHAV；
18、完成T?触发器的设计。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL； ENTITY DFF IS
PORT(CLK，RESET:IN STD_LOGIC; Q:INOUT STD_LOGIC); END DFF;
ARCHITECTURE BEHAV OF DFF IS BEGIN
PROCESS(CLK) BEGIN
IF CLK?EVENT AND CLK=?1?THEN Q<=NOT Q;
END IF; END PROCESS; END BEHAV；
19、完成带同步清零端子的T?触发器的设计。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL； ENTITY DFF IS
PORT(CLK，RESET:IN STD_LOGIC; Q:INOUT STD_LOGIC); END DFF;
ARCHITECTURE BEHAV OF DFF IS BEGIN
PROCESS(CLK,RESET) BEGIN
IF CLK?EVENT AND CLK=?1?THEN ELSIF RESET=?1? THEN Q<=?0?; ELSE Q<=NOT Q;
END IF; END PROCESS; END BEHAV；
20、完成带异步清零端子的T?触发器的设计。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL； ENTITY DFF IS
PORT(CLK，RESET:IN STD_LOGIC; Q:INOUT STD_LOGIC); END DFF;